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TFP201PZP Datasheet(PDF) 11 Page - Texas Instruments |
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TFP201PZP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 18 page TFP201, TFP201A TI PanelBus DIGITAL RECEIVER SLDS116A - MARCH 2000 – REVISED JUNE 2000 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) TFP201/201A clocking and data synchronization The TFP201/201A receives a clock reference from the TMDS transmitter that has a period equal to the pixel time, Tpix. The frequency of this clock is also referred to as the pixel rate. Since the TMDS encoded data on Rx[2:0] contains 10 bits per 8 bit pixel it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the required pixel rate to support an SXGA resolution with 60 Hz refresh rate is 112 MHz. The TMDS serial bit rate is 10x the pixel rate or 1.12 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate channels (or twisted-pair wires) of long distances (3-5 meters), phase synchronization between the data steams and the input reference clock is not guaranteed. In addition, skew between the three data channels is common. The TFP201/201A uses a 4x oversampling scheme of the input data streams to achieve reliable synchronization with up to 1-Tpix channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of high speed serial data transmission, hence the TFP201/201A’s design for high jitter tolerance. The input clock to the TFP201/201A is conditioned by a phase-locked-loop (PLL) to remove high frequency jitter from the clock. The PLL provides four 10x clock outputs of different phase to locate and sync the TMDS data streams (4x oversampling). During active display the pixel data is encoded to be transition minimized, whereas in blank, the control data is encoded to be transition maximized. A DVI compliant transmitter is required to transmit in blank for a minimum period of time, 128-Tpix, to ensure sufficient time for data synchronization when the receiver sees a transition maximized code. Synchronization during blank, when the data is transition maximized, ensures reliable data bit boundary detection. Phase synchronization to the data streams is unique for each of the three input channels and is maintained as long as the link remains active. TFP201/201A TMDS input levels and input impedance matching The TMDS inputs to the TFP201/201A receiver have a fixed single-ended termination to AVDD The TFP201/201A is internally optimized using a laser trim process to precisely fix the impedance at 50 Ω. The device will function normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets. The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching to standard 50- Ω DVI cables. Figure 14 shows a conceptual schematic of a DVI transmitter and TFP201/201A receiver connection. A transmitter drives the twisted pair cable via a current source, usually achieved with an open drain type output driver. The internal resistor, which is matched to the cable impedance, at the TFP201/201A input provides a pullup to AVDD . Naturally, when the transmitter is disconnected and the TFP201/201A DVI inputs are left unconnected, the TFP201/201A receiver inputs pullup to AVDD. The single ended differential signal and full differential signal is shown in Figure 15. The TFP201/201A is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with common mode voltages ranging from (AVDD-300 mV) to (AVDD-37 mV). |
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