LMK04828SNKDTEP datasheet(4/102 Pages) TI1

Part #	LMK04828SNKDTEP

Description	Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

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Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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4

LMK04828-EP

SNAS703 – APRIL 2017

www.ti.com

Product Folder Links: LMK04828-EP

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Pin Functions (continued)

I/O

TYPE

DESCRIPTION

(1)

NO.

NAME

6

SYNC/SYSREF_REQ

I

CMOS

Synchronization input or SYSREF_REQ for requesting continuous SYSREF

7, 8, 9

NC

Do not connect. These pins must be left floating.

10

Vcc1_VCO

PWR

Power supply for VCO LDO

11

LDObyp1

ANLG

LDO bypass, bypassed to ground with 10-µF capacitor.

12

LDObyp2

ANLG

LDO bypass, bypassed to ground with a 0.1-µF capacitor.

13

14

SDCLKout3,

SDCLKout3*

O

Programmable

SYSREF or device clock output 3

15

16

DCLKout2,

DCLKout2*

O

Programmable

Device clock output 2

17

Vcc2_CG1

PWR

Power supply for clock outputs 2 and 3

18

CS*

I

CMOS

Chip select

19

SCK

I

CMOS

SPI clock

20

SDIO

I/O

CMOS

SPI data

21

Vcc3_SYSREF

PWR

Power supply for SYSREF divider and SYNC

22

23

SDCLKout5,

SDCKLout5*

O

Programmable

SYSREF or device clock output 5

24

25

DCLKout4,

DCLKout4*

O

Programmable

Device clock output 4

26

Vcc4_CG2

PWR

Power supply for clock outputs 4, 5, 6 and 7

27

28

DCLKout6,

DCLKout6*

O

Programmable

Device clock output 6

29

30

SDCLKout7,

SDCLKout7*

O

Programmable

SYSREF or device clock output 7

31

Status_LD1

I/O

Programmable

Programmable status pin

32

CPout1

O

ANLG

Charge pump 1 output

33

Vcc5_DIG

PWR

Power supply for the digital circuitry

34

35

CLKin1, CLKin1*

I

ANLG

Reference clock Input Port 1 for PLL1

FBCLKin,

FBCLKin*

I

ANLG

Feedback input for external clock feedback input (0–delay mode)

Fin, Fin*

I

ANLG

External VCO input (external VCO mode)

36

Vcc6_PLL1

PWR

Power supply for PLL1, charge pump 1, holdover DAC

37

38

CLKin0, CLKin0*

I

ANLG

Reference clock input port 0 for PLL1

39

Vcc7_OSCout

PWR

Power supply for OSCout port

40

41

OSCout, OSCout*

I/O

Programmable

Buffered output of OSCin port

CLKin2, CLKin2*

Reference clock Input Port 2 for PLL1

42

Vcc8_OSCin

PWR

Power supply for OSCin

43

44

OSCin, OSCin*

I

ANLG

Feedback to PLL1, reference input to PLL2 — AC-coupled

45

Vcc9_CP2

PWR

Power supply for PLL2 charge pump

46

CPout2

O

ANLG

Charge pump 2 output

47

Vcc10_PLL2

PWR

Power supply for PLL2

48

Status_LD2

I/O

Programmable

Programmable status pin

49

50

SDCLKout9,

SDCLKout9*

O

Programmable

SYSREF or device clock 9

51

52

DCLKout8,

DCLKout8*

O

Programmable

Device clock output 8

53

Vcc11_CG3

PWR

Power supply for clock outputs 8, 9, 10, and 11

54

55

DCLKout10,

DCLKout10*

O

Programmable

Device clock output 10

56

57

SDCLKout11,

SDCLKout11*

O

Programmable

SYSREF or device clock output 11

58

CLKin_SEL0

I/O

Programmable

Programmable status pin

59

CLKin_SEL1

I/O

Programmable

Programmable status pin

60

61

SDCLKout13,

SDCLKout13*

O

Programmable

SYSREF or device clock output 13

62

63

DCLKout12,

DCLKout12*

O

Programmable

Device clock output 12

64

Vcc12_CG0

PWR

Power supply for clock outputs 0, 1, 12, and 13

DAP

GND

DIE ATTACH PAD, connect to GND

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LMK04828SNKDTEP Datasheet(PDF) 4 Page - Texas Instruments

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