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DRV8320SRTVR Datasheet(PDF) 8 Page - Texas Instruments |
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DRV8320SRTVR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 89 page 8 DRV8320, DRV8320R DRV8323, DRV8323R SLVSDJ3A – FEBRUARY 2017 – REVISED APRIL 2017 www.ti.com Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions—48-Pin DRV8323R Devices (continued) PIN TYPE (1) DESCRIPTION NAME NO. DRV8323RH DRV8323RS CB 44 44 PWR Buck regulator bootstrap input. Connect a X5R or X7R, 0.1-µF, 16-V, capacitor between the CB and SW pins. CPH 4 4 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. CPL 3 3 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VM-rated ceramic capacitor between the CPH and CPL pins. DGND 27 27 PWR Device ground. Connect to system ground. DVDD 36 36 PWR 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally. ENABLE 33 33 I Gate driver enable. When this pin is logic low the device enters a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions. FB 1 1 I Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage. GAIN 32 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor. GHA 8 8 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GHB 17 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GHC 18 18 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. GLA 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. GLB 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. GLC 20 20 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. IDRIVE 30 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. INHA 37 37 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INHB 39 39 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INHC 41 41 I High-side gate driver control input. This pin controls the output of the high-side gate driver. INLA 38 38 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLB 40 40 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. INLC 42 42 I Low-side gate driver control input. This pin controls the output of the low-side gate driver. MODE 29 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor. NC 46 46 NC No internal connection. This pin can be left floating or connected to system ground. nFAULT 28 28 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. nSCS — 32 I Serial chip select. A logic low on this pin enables serial interface communication. nSHDN 48 48 I Buck shutdown input. Enable and disable input (high voltage tolerant). Internal pullup current source. Pull below 1.25 V to disable. Float to enable. Establish input undervoltage lockout with two resistor divider. PGND 2 2 PWR Device power ground. Connect to system ground. SCLK — 31 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. SDI — 30 I Serial data input. Data is captured on the falling edge of the SCLK pin. SDO — 29 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. SHA 9 9 I High-side source sense input. Connect to the high-side power MOSFET source. SHB 16 16 I High-side source sense input. Connect to the high-side power MOSFET source. SHC 19 19 I High-side source sense input. Connect to the high-side power MOSFET source. SNA 12 12 I Shunt amplifier input. Connect to the low-side of the current shunt resistor. SNB 13 13 I Shunt amplifier input. Connect to the low-side of the current shunt resistor. SNC 22 22 I Shunt amplifier input. Connect to the low-side of the current shunt resistor. SOA 25 25 O Shunt amplifier output. SOB 24 24 O Shunt amplifier output. SOC 23 23 O Shunt amplifier output. SPA 11 11 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. SPB 14 14 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. SPC 21 21 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. SW 45 45 O Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor. VCP 5 5 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins. VDRAIN 7 7 I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains. VDS 31 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. VIN 47 47 PWR Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins. VM 6 6 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins. VREF 26 26 PWR Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins. |
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