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TMS320VC5510A Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320VC5510A Datasheet(HTML) 11 Page - Texas Instruments |
11 / 90 page Features 11 June 2000 − Revised September 2007 SPRS076O 1 Features D High-Performance, Low-Power, Fixed-Point TMS320C55x Digital Signal Processor (DSP) − 6.25-/5-ns Instruction Cycle Time − 160-/200-MHz Clock Rate − One/Two Instructions Executed per Cycle − Dual Multipliers (Up to 400 Million Multiply-Accumulates Per Second (MMACS)) − Two Arithmetic/Logic Units − One Internal Program Bus − Three Internal Data/Operand Read Buses − Two Internal Data/Operand Write Buses D Instruction Cache (24K Bytes) D 160K x 16-Bit On-Chip RAM Composed of: − Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes) − 32 Blocks of 4K × 16-Bit Single-Access RAM (SARAM) (256K Bytes) D 16K × 16-Bit On-Chip ROM (32K Bytes) D 8M × 16-Bit Maximum Addressable External Memory Space D 32-Bit External Memory Interface (EMIF) With Glueless Interface to: − Asynchronous Static RAM (SRAM) − Asynchronous EPROM − Synchronous DRAM (SDRAM) − Synchronous Burst SRAM (SBSRAM) D Programmable Low-Power Control of Six Device Functional Domains D On-Chip Peripherals − Two 20-Bit Timers − Six-Channel Direct Memory Access (DMA) Controller − Three Multichannel Buffered Serial Ports (McBSPs) − 16-Bit Parallel Enhanced Host-Port Interface (EHPI) − Programmable Digital Phase-Locked Loop (DPLL) Clock Generator − Eight General-Purpose I/O (GPIO) Pins and Dedicated General-Purpose Output (XF) D On-Chip Scan-Based Emulation Logic D IEEE Std 1149.1† (JTAG) Boundary Scan Logic D 240-Terminal MicroStar BGA (Ball Grid Array) (GGW Suffix) D 240-Terminal MicroStar BGA (Ball Grid Array) (ZGW Suffix) [Lead-Free] D 3.3-V I/O Supply Voltage D 1.6-V Core Supply Voltage TMS320C55x and MicroStar BGA are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. |
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