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AD5318 Datasheet(PDF) 5 Page - Analog Devices |
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AD5318 Datasheet(HTML) 5 Page - Analog Devices |
5 / 19 page REV. B AD5308/AD5318/AD5328 –5– PIN CONFIGURATION TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 SYNC LDAC VDD VOUTA VOUTB VOUTC VOUTD VREFABCD SCLK DIN VOUTE AD5308/ AD5318/ AD5328 VREFEFGH VOUTF VOUTG VOUTH GND PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 LDAC This active low-control input transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. 2 SYNC Active Low-Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4VOUTABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 5VOUTBBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 6VOUTCBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 7VOUTDBuffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 8VREFABCD Reference Input Pin for DACs A, B, C, and D. It may be configured as a buffered, unbuffered, or VDD input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 9VREFEFGH Reference Input Pin for DACs E, F, G, and H. It may be configured as a buffered, unbuffered, or VDD input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 10 VOUTEBuffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. 11 VOUTFBuffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. 12 VOUTGBuffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. 13 VOUTHBuffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. 14 GND Ground Reference Point for All Circuitry on the Part. 15 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. |
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