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TP3155 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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TP3155 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 10 page  Absolute Maximum Ratings If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications VCC Relative to GND 7V Voltage at Any Input or Output VCC a 03V to GND b03V Operating Temperature Range (Ambient) b 25 Cto a125 C Storage Temperature Range (Ambient) b 65 Cto a150 C Maximum Lead Temperature (Soldering 10 seconds) 300 C ESD rating to be determined DC Electrical Characteristics Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e 50V g5% TA e 0 Cto a70 Cby correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization Typicals specified at VCC e 50V TA e 25 C Parameter Conditions Min Typ Max Units Input Voltage Levels VIH Logic High 20 V VIL Logic Low 07 V Input Currents All Inputs Except MODE VIL k VIN k VIH b 11 m A MODE VIN e 0V b 100 m A Output Voltage Levels VOH Logic High FSX and FSR Outputs IOH e 3 mA 24 V VOL Logic Low FSX and FSR Outputs IOL e 5 mA 04 V TSX Output IOL e 5mA 04 V Power Dissipation BCLK e 2048 MHz 1 15 mA Operating Current All Outputs Open-Circuit Timing Specifications Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e 50V g5% TA e 0 Cto a70 Cby correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization Typicals specified at VCC e 50V TA e 25 C All timing parameters are measured at VOH e 20V and VOL e 07V See Definitions and Timing Conventions section for test methods information Symbol Parameter Conditions Min Max Units tPC Period of Clock BCLK CLKC 480 ns tWCH Width of Clock High BCLK CLKC 160 ns tWCL Width of Clock Low BCLK CLKC 160 ns tSDC Set-Up Time from DC to CLKC 50 ns tHCD Hold Time from CLKC to DC 50 ns tSCC Set-Up Time from CS to CLKC 30 ns tHCC Hold Time from CLKC to CS 100 ns tSCHC Set-Up Time from Channel Select to CLKC 50 ns tHCHC Hold Time from Channel Select to CLKC 50 ns tDBF Delay Time from BCLK Low to FSXR 0–3 CL e 50 pF 100 ns High or Low tHSYNC Hold Time from BCLK to Frame Sync 50 ns tSSYNC Set-Up Time from Frame Sync to BCLK 100 ns tDTL Delay to TSX Low CL e 50 pF 140 ns tDTH Delay to TSX High RL e 1k to VCC 30 140 ns tRC tFC Rise and Fall Time of Clock BCLK CLKC 50 ns 2 |
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Similar Description - TP3155 |
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