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TPL0401A Datasheet(PDF) 6 Page - Texas Instruments |
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TPL0401A Datasheet(HTML) 6 Page - Texas Instruments |
6 / 33 page 6 TPL0401A TPL0401B SLIS144B – SEPTEMBER 2011 – REVISED FEBRUARY 2017 www.ti.com Product Folder Links: TPL0401A TPL0401B Submit Documentation Feedback Copyright © 2011–2017, Texas Instruments Incorporated 7.6 Timing Requirements MIN MAX UNIT STANDARD MODE fSCL I2C clock frequency 0 100 kHz tSCH I2C clock high time 4 µs tSCL I2C clock low time 4.7 µs tsp I2C spike time 0 50 ns tSDS I2C serial data setup time 250 ns tSDH I2C serial data hold time 0 ns tICR I2C input rise time 1000 ns tICF I2C input fall time 300 ns tOCF I2C output fall time, 10 pF to 400 pF bus 300 ns tBUF I2C bus free time between stop and start 4.7 µs tSTS I2C start or repeater start condition setup time 4.7 µs tSTH I2C start or repeater start condition hold time 4 µs tSPS I2C stop condition setup time 4 µs tVD(DATA) Valid data time, SCL low to SDA output valid 1 µs tVD(ACK) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 1 µs FAST MODE fSCL I2C clock frequency 0 400 kHz tSCH I2C clock high time 0.6 µs tSCL I2C clock low time 1.3 µs tsp I2C spike time 0 50 ns tSDS I2C serial data setup time 100 ns tSDH I2C serial data hold time 0 ns tICR I2C input rise time 20 300 ns tICF I2C input fall time 20 × (VDD / 5.5) 300 ns tOCF I2C output fall time, 10 pF to 400 pF bus (VDD / 5.5) × 20 300 ns tBUF I2C bus free time between stop and start 1.3 µs tSTS I2C start or repeater start condition setup time 1.3 µs tSTH I2C start or repeater start condition hold time 0.6 µs tSPS I2C stop condition setup time 0.6 µs tVD(DATA) Valid data time, SCL low to SDA output valid 1 µs tVD(ACK) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 1 µs |
Similar Part No. - TPL0401A_17 |
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Similar Description - TPL0401A_17 |
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