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AT84AD004 Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT84AD004 Datasheet(HTML) 2 Page - ATMEL Corporation |
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2 / 58 page  2 AT84AD004 5390A–BDC–06/04 Description The AT84AD004 is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power consumption and excellent digitizing accuracy. It integrates dual on-chip track/holds that provide an enhanced dynamic performance with a sampling rate of up to 500 Msps and an input frequency bandwidth of 1 GHz. The dual concept, the integrated demultiplexer and the easy interleaving mode make this device user-friendly for all dual channel applications, such as direct RF conversion or data acquisition. The smart func- tion of the 3-wire serial interface eliminates the need for external components, which are usually necessary for gain and offset tuning and setting of other parameters, leading to space and power reduction as well as system flexibility. Functional Description The AT84AD004 is a dual 8-bit 500 Msps ADC based on advanced high-speed BiCMOS technology. Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H), and an 8-bit flash-like architecture core analog-to-digital converter. The output data is followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100 Ω). Two over-range bits are provided for adjustment of the external gain control on each channel. A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several adjustments: • Analog input range adjustment (±1.5 dB) with 8-bit data control using a 3-wire bus interface (steps of 0.18 dB) • Analog input switch: both ADCs can convert the same analog input signal I or Q • Gray or binary encoder output. Output format: DMUX 1:1 or 1:2 with control of the output frequency on the data ready output signal • Partial or full standby on channel I or channel Q • Clock selection: – Two independent clocks: CLKI and CLKQ – One master clock (CLKI) with the same phase for channel I and channel Q – One master clock but with two phases (CLKI for channel I and CLKIB for channel Q) • ISA: Internal Settling Adjustment on channel I and channel Q • FiSDA: Fine Sampling Delay Adjustment on channel Q • Adjustable Data Ready Output Delay on both channels • Test mode: decimation mode (by 16), Built-in Test A calibration phase is provided to set the two DC offsets of channel I and channel Q close to code 127.5 and calibrate the two gains to achieve a maximum difference of 0.5 LSB. The offset and gain error can also be set externally via the 3-wire serial interface. The AT84AD004 operates in fully differential mode from the analog inputs up to the dig- ital outputs. The AT84AD004 features a full-power input bandwidth of 1 GHz. |
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