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TPS3808G125 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS3808G125 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 32 page  6 5 4 1 2 3 RESET GND MR C T SENSE V DD THERMAL PAD 1 2 3 6 5 4 RESET GND MR C T SENSE V DD 4 TPS3808 SBVS050K – MAY 2004 – REVISED OCTOBER 2015 www.ti.com Product Folder Links: TPS3808 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated 6 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View DRV Package 6-Pin (2.00 mm × 2.00 mm) WSON With Thermal Pad Top View Pin Functions PIN I/O DESCRIPTION NAME SOT-23 WSON CT 4 3 I Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the RESET Delay Time section for more information. GND 2 5 — Ground MR 3 4 I Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90- k Ω pull-up resistor. RESET 1 6 O RESET is an open-drain output that is driven to a low-impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. SENSE 5 2 I This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted. VDD 6 1 I Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin. Thermal Pad — Pad — Thermal Pad. Connect to ground plane to enhance thermal performance of package. |
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