Feed Forward Gain +

VIN

Ramp

pk*pk

11

TPS5430, TPS5431

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SLVS632I – JANUARY 2006 – REVISED APRIL 2017

Product Folder Links: TPS5430 TPS5431

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Copyright © 2006–2017, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Oscillator Frequency

The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching

frequency allows less output inductance for the same output ripple requirement resulting in a smaller output

inductor.

7.3.2 Voltage Reference

The voltage reference system produces a precision reference signal by scaling the output of a temperature

stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of

1.221 V at room temperature.

7.3.3 Enable (ENA) and Internal Slow Start

The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold

voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled

below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin

to ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. The

quiescent current of the TPS543x in shutdown mode is typically 18 μA.

The ENA pin has an internal pull-up current source, allowing the user to float the ENA pin. If an application

requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit

the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its

final value, linearly. The internal slow start time is 8 ms typically.

7.3.4 Undervoltage Lockout (UVLO)

The TPS543x incorporate an undervoltage lockout circuit to keep the device disabled when VIN (the input

voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the

internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start

threshold voltage is reached, the internal slow start is released and device start-up begins. The device operates

until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.

7.3.5 Boost Capacitor (BOOT)

Connect a 0.01 μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the

gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable

values over temperature.

7.3.6 Output Feedback (VSENSE) and Internal Compensation

The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider

network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage

reference 1.221 V.

The TPS543x implements internal compensation to simplify the regulator design. Since the TPS543x uses

voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover

frequency and a high phase margin for good stability. See the Internal Compensation Network in the applications

section for more details.

7.3.7 Voltage Feed-Forward

The internal voltage feed-forward provides a constant dc power stage gain despite any variations with the input

voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward

varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are

constant at the feed forward gain, i.e.

(1)

The typical feed forward gain of TPS543x is 25.