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TPS3808G15DRVT Datasheet(PDF) 11 Page - Texas Instruments |
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TPS3808G15DRVT Datasheet(HTML) 11 Page - Texas Instruments |
11 / 32 page C T (nF) t D (s) 0.5 10 3 (s) 175 = [ ] – × × - Delay (s) = CT (nF) + 0.5 x 10−3 (s) 20ms Delay 300ms Delay (c) (b) (a) 175 3.3V TPS3808G33 V DD SENSE C T RESET 3.3V TPS3808G33 V DD SENSE C T C T RESET 3.3V TPS3808G33 V DD SENSE C T 50k Ω RESET V IN TPS3808G01 V DD SENSE GND RESET R 1 R 2 1nF V =(1+)0.405 IT ¢ R1 R2 V OUT 11 TPS3808 www.ti.com SBVS050K – MAY 2004 – REVISED OCTOBER 2015 Product Folder Links: TPS3808 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Feature Description (continued) Figure 9. Using the TPS3808G01 to Monitor a User-Defined Threshold Voltage 8.3.2 Selecting the RESET Delay Time The TPS3808 has three options for setting the RESET delay time as shown in Figure 10. Figure 10 (a) shows the configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must be used. Supply current is not affected by the choice of resistor. Figure 10 (b) shows a fixed 20-ms delay time by leaving the CT pin open. Figure 10 (c) shows a ground referenced capacitor connected to CT for a user-defined program time between 1.25 ms and 10 s. Figure 10. Configuration Used to Set the RESET Delay Time The capacitor CT should be ≥ 100 pF nominal value in order for the TPS3808xxx to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using Equation 1. (1) The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the external capacitor to 1.23 V. When a RESET is asserted, the capacitor is discharged. When the RESET conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When the voltage on this capacitor reaches 1.23 V, RESET is deasserted. Note that a low-leakage type capacitor such as a ceramic should be used, and that stray capacitance around this pin may cause errors in the reset delay time. |
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