AT94S10AL-25BQI datasheet(5/31 Pages) ATMEL

Part #	AT94S10AL-25BQI

Description	Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM

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Manufacturer	ATMEL [ATMEL Corporation]

Direct Link	http://www.atmel.com

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5

AT94S Secure Family

2314D–FPSLI–2/04

Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a

byte-by-byte basis.

The factory blanks devices to all zeros before shipping. The array cannot otherwise be

“initialized” except by explicitly writing a known value to each location using the serial

protocol described herein.

Bit Format

Data on the cSDA pin may change only during the cSCK Low time; whereas Start and

Stop Conditions are identified as transitions during the cSCK High time.

Write Instruction Message Format

Current Address Read (Extended to Sequential Read) Instruction Message Format

Start and Stop

Conditions

The Start Condition is indicated by a high-to-low transition of the cSDA line when the

cSCK line is High. Similarly, the Stop Condition is generated by a low-to-high transition

of the cSDA line when the cSCK line is High, as shown in Figure 2.

The Start Condition will return the device to the state where it is waiting for a Device

Address (its normal quiescent mode).

The Stop Condition initiates an internally timed write signal whose maximum duration is

t

WR (refer to AC Characteristics table for actual value). During this time, the Configurator

must remain in programming mode (i.e., SER_EN is driven Low). cSDA and cSCK lines

are ignored until the cycle is completed. Since the write cycle typically completes in less

than t

WR seconds, we recommend the use of “polling” as described in later sections.

Input levels to all other pins should be held constant until the write cycle has been

completed.

Acknowledge Bit

The Acknowledge (ACK) Bit shown in Figure 2 is provided by the Configurator receiving

the byte. The receiving Configurator can accept the byte by asserting a Low value on

the cSDA line, or it can refuse the byte by asserting (allowing the signal to be externally

pulled up to) a High value on the cSDA line. All bytes from accepted messages must be

terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit,

when the cSDA line is released during an exchange of control between the Configurator

and the programmer, the cSDA line may be pulled High temporarily due to the open-col-

lector output nature of the line. Control of the line must resume before the next rising

edge of the clock.

ACK BIT

(CONFIGURATOR)

DATA

BYTE n

STOP

CONDITION

START

CONDITION

DEVICE

ADDRESS

MS EEPROM

ADDRESS BYTE

(NEXT) EEPROM

ADDRESS BYTE

LS EEPROM

ADDRESS BYTE

DATA

BYTE 1

ACK BIT

(CONFIGURATOR)

DATA

BYTE n

STOP

CONDITION

START

CONDITION

DEVICE

ADDRESS

DATA

BYTE 1

ACK BIT

(PROGRAMMER)

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AT94S10AL-25BQI Datasheet(PDF) 5 Page - ATMEL Corporation

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