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SN24710DGS Datasheet(PDF) 2 Page - Texas Instruments |
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SN24710DGS Datasheet(HTML) 2 Page - Texas Instruments |
2 / 38 page 2 TPS24710, TPS24711 TPS24712, TPS24713 SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015 www.ti.com Product Folder Links: TPS24710 TPS24711 TPS24712 TPS24713 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Table of Contents 1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Device Comparison Table..................................... 4 6 Pin Configuration and Functions ......................... 4 7 Specifications......................................................... 5 7.1 Absolute Maximum Ratings ...................................... 5 7.2 ESD Ratings ............................................................ 5 7.3 Recommended Operating Conditions ....................... 5 7.4 Thermal Information ................................................. 5 7.5 Electrical Characteristics........................................... 6 7.6 Timing Requirements ................................................ 7 7.7 Typical Characteristics .............................................. 9 8 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 17 9 Application and Implementation ........................ 24 9.1 Application Information............................................ 24 9.2 Typical Application ................................................. 24 10 Power Supply Recommendations ..................... 30 11 Layout................................................................... 31 11.1 Layout Guidelines ................................................. 31 11.2 Layout Example .................................................... 31 12 Device and Documentation Support ................. 32 12.1 Documentation Support ....................................... 32 12.2 Related Links ........................................................ 32 12.3 Community Resources.......................................... 32 12.4 Trademarks ........................................................... 32 12.5 Electrostatic Discharge Caution ............................ 32 12.6 Glossary ................................................................ 32 13 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (February 2015) to Revision G Page • Changed the values of the Power limit threshold in Electrical Characteristics for VOUT = 7 V and VOUT = 2 V From: 10, 12.5, 15 mV To: 10.1, 11.6, 13.1 mV ............................................................................................................................... 7 • Changed the title of Figure 8 From: MOSFET Gate Current vs Voltage Across RSENSE During Inrush Power Limiting To: Gate Current vs Voltage Across RSENSE........................................................................................................................... 9 • Added Figure 9 ...................................................................................................................................................................... 9 • Changed V(VCC–SENSE) To: V(SENSE–VCC) in Figure 10 and Figure 11 ........................................................................................ 9 • Added Equation 1 ................................................................................................................................................................ 15 • Added text to the PROG section: "To compute the Power limit based on an existing RPROG..." ......................................... 15 • Changed Equation 2 ............................................................................................................................................................ 15 • Changed text in STEP 3. Choose Power-Limit Value, PLIM, and RPROG From: "a 53.6-kΩ, 1% resistor is selected for RPROG" To: a 44.2-kΩ, 1% resistor is selected for RPROG" .................................................................................................... 27 • Changed Equation 9 ............................................................................................................................................................ 27 • Added the Using Soft Start with TPS2471x section ............................................................................................................ 30 Changes from Revision E (November 2013) to Revision F Page • Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 • Changed the Input voltage range, PROG - MAX value in the Absolute Maximum Ratings table From: 0.3 To: 3.6 ............ 5 • Deleted External capacitance - GATE from the Recommended Operating Conditions ......................................................... 5 • Deleted text from the last paragraph in the GATE section "If used, any capacitor connecting GATE and GND should not exceed 1 μF and it should be connected in series with a resistor of no less than 1 kΩ.".............................................. 15 • Deleted section: Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush Mode......................................... 29 • Deleted text from the High-Gate-Capacitance Applications section "When gate capacitor dV/dt control is used, ... then a Zener diode is not necessary." .................................................................................................................................. 29 |
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