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CH7006C-V Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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CH7006C-V Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 49 page  201-0000-026 Rev 2.1, 8/2/99 9 CHRONTEL CH7006C Multiplexed Mode Each rising edge (or each rising and falling edge) of the XCLK signal will latch data from the graphics chip. The multiplexed input data formats are shown in Figure 5 and 6. The Pixel Data bus represents an 8, 12, or 16-bit multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 2, 4, 5, 7, 8 and 9, the input data rate is 2X PCLK, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the tables below. When IDF = 6, the input data rate is 3X PCLK, and each triplet of Pn values (e.g., P0a, P0b and P0c) will contain a complete pixel, encoded as shown in the tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples — and the following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is dependent upon the current mode, (not 27MHz, as specified in CCIR656). Figure 5: Multiplexed Pixel Data Transfer Mode Table 4. RGB 8-bit Multiplexed Mode IDF# Format 7 RGB 5-6-5 8 RGB 5-5-5 Pixel# P0a P0b P1a P1b P0a P0b P1a P1b Bus Data D[7] G0[2] R0[4] G1[2] R1[4] G0[2] x G1[2] x D[6] G0[1] R0[3] G1[1] R1[3] G0[1] R0[4] G1[1] R1[4] D[5] G0[0] R0[2] G1[0] R1[2] G0[0] R0[3] G1[0] R1[3] D[4] B0[4] R0[1] B1[4] R1[1] B0[4] R0[2] B1[4] R1[2] D[3] B0[3] R0[0] B1[3] R1[0] B0[3] R0[1] B1[3] R1[1] D[2] B0[2] G0[5] B1[2] G1[5] B0[2] R0[0] B1[2] R1[0] D[1] B0[1] G0[4] B1[1] G1[4] B0[1] G0[4] B1[1] G1[4] D[0] B0[0] G0[3] B1[0] G1[3] B0[0] G0[3] B1[0] G1[3] t HSW HS t HD t PH2 t P2 t HP2 t SP2 D[15:0] P0a P0b P1a P1b P2a P2b XCLK DEC = 0 XCLK DEC = 1 t SP2 t SP2 t HP2 t HP2 |
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