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82P33814ANLG Datasheet(PDF) 1 Page - Integrated Device Technology |
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82P33814ANLG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 12 page This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on the last page. 5 ©2017 Integrated Device Technology, Inc. Revision 7, January 9, 2017 HIGHLIGHTS • Synchronization Management Unit (SMU) provides tools to man- age physical layer and packet based synchronous clocks for IEEE 1588 / PTP Telecom Profile applications • Supports independent IEEE 1588 and Synchronous Ethernet (SyncE) timing paths • Combo mode provides SyncE physical layer frequency support for IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time Slave Clocks (T-TSC) per G.8273.2 • Digital PLL 1 (DPLL1) and DPLL 2 can be configured as Digitally Controlled Oscillators (DCOs) for PTP clock synthesis • DCO frequency resolution is [(77760 / 1638400) * 2^-48] or ~1.686305041e-10 ppm • DPLL1 and DPLL2 generate G.8262 compliant SyncE clocks • Two independent Time of Day (ToD) counters/time accumulators, one associated with each of DPLL1 and DPLL2, can be used to track differences between the two time domains and to time-stamp external events • DPLL3 performs rate conversions to frequency synchronization interfaces or for other general purpose timing applications • APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to 20 MHz) for: 1000BASE-T and 1000BASE-X • Fractional-N input dividers support a wide range of reference fre- quencies • Locks to 1 Pulse Per Second (PPS) references • It can be configured from an external EEPROM after reset FEATURES • Differential reference inputs (IN1 to IN4) accept clock frequencies between 1 PPS and 650 MHz • Single ended inputs (IN5 to IN6) accept reference clock frequen- cies between 1 PPS and 162.5 MHz • Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input • Reference monitors qualify/disqualify references depending on activity, frequency and LOS pins • Automatic reference selection state machines select the active ref- erence for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programma- ble settings • Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/1000 Ether- net, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI and GNSS frequencies • Any reference input (IN1 to IN6) can be designated as external sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a selectable reference clock input • FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses that are aligned with the selected external input sync pulse input and frequency locked to the associated reference clock input • DPLL1 and DPLL2 can be configured with bandwidths between 0.09 mHz and 567 Hz • DPLL1 and DPLL2 lock to input references with frequencies between 1 PPS and 650 MHz • DPLL3 locks to input references with frequencies between 8 kHz and 650 MHz • DPLL1 and DPLL2 comply with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC); and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC) • DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/ OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks are directly available on OUT1 and OUT8 • DPLL1 and DPLL2 can be configured as DCOs to synthesize IEEE 1588 clocks • DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on OUT9 and OUT10 • APLL1 and APLL2 can be connected to DPLL1 or DPLL2 • APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or SONET/SDH frequencies • Any of eight common TCXO/OCXO frequencies can be used for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz • The I2C slave, SPI or the UART interface can be used by a host processor to access the control and status registers • The I2C master interface can automatically load a device configura- tion from an external EEPROM after reset • Differential outputs OUT3 to OUT6 output clocks with frequencies between 1 PPS and 650 MHz • Single ended outputs OUT1, OUT2, OUT7 and OUT8 output clocks with frequencies between 1 PPS and 125 MHz • Single ended outputs OUT9 and OUT10 output clocks N*8kHz mul- tiples up to 100 MHz • DPLL1 and DPLL2 support independent programmable delays for each of IN1 to IN6; the delay for each input is programmable in steps of 0.61 ns with a range of ~±78 ns • The input to output phase delay of DPLL1 and DPLL2 is program- mable in steps of 0.0745 ps with a total range of ±20 μs • The clock phase of each of the output dividers for OUT1 (from APLL1) to OUT8 is individually programmable in steps of ~200 ps with a total range of +/-180° • 1149.1 JTAG Boundary Scan • 72-pin QFN green package APPLICATIONS • Access routers, edge routers, core routers • Carrier Ethernet switches • Multiservice access platforms • PON OLT • LTE eNodeB • IEEE 1588 / PTP Telecom Profile clock synthesizer • ITU-T G.8273.2 Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) • ITU-T G.8264 Synchronous Equipment Timing Source (SETS) • ITU-T G.8263 Packet-based Equipment Clock (PEC) Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet 82P33814 Datasheet |
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