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CS6420 Datasheet(PDF) 11 Page - Cirrus Logic

Part No. CS6420
Description  FULL DUPLEX SPEAKERPHONE CHIP
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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CS6420
DS205PP2
11
to shift the next bit into the shift register. The next
data bit should then be presented to the DATA pin
ready to be latched by the rising edge of STROBE.
This procedure repeats for all sixteen bits as shown
in Figure 5. After the last bit has been shifted in,
DRDY should be brought high to indicate the con-
clusion of the transfer, and four extra STROBE
pulses must be applied to latch the data into the
CS6420.
Since the MCR is a shift register, the STROBE can
be run arbitrarily slow with a duty cycle limited
only by the hold time specified in the Switching
Characterstics table. The Microcontroller Interface
is read once every 125
µs, so it must not be updated
faster than this.
Register Definitions
The four control registers accessible through the
MCR are described in detail in the following tables.
These registers are addressed by bits b2 and b1 of
the MCR. Bit b0 must always be 0. Table 2 shows
the relative bit positions of all the registers. Tables
3 to 6 show the four control registers in more detail.
The Register Map at the top of each register de-
scription shows the names of all the bits, with their
reset values below the bitfield name. The reset val-
ue can also be found in the Word column of the bit-
field summary as indicated by an ‘*’.
Table 2. MCR Control Register Mapping
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Mic
TSD
GB
ACC
RVol
TGain
0
0
0
HD
RSD
Taps
NCC
TVol
RGain
0
1
0
NErle
NFNse
RHDet
HDly
NseRmp
RSThd
PCSen
1
0
0
AErle
AFNse
THDet
TSAtt
TSBias
TSThd
HHold
1
1
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DATA
DRDY
STROBE
12
34
four extra strobe pulses
Figure 5. Microcontroller Interface




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