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84321I Datasheet(PDF) 10 Page - Integrated Device Technology |
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84321I Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 18 page  260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 84321I DATA SHEET 10 REVISION B 11/5/15 The schematic of the 84321I layout example used in this layout guideline is shown in Figure 5A. The 84321I recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the LAYOUT GUIDELINE FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 84321I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, VCCA, and V CCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 4 illustrates how a 24 Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V CCA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 4. POWER SUPPLY FILTERING 24 Ω V CCA 10 μF .01 μF 3.3V .01 μF V CC R4 84 + - VCCA U1 ICS84321 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 M5 M6 M7 M8 N0 N1 nc VEE MR S_CLOCK S_DATA S_LOAD VCCA nXTAL_SEL T_CLK XTAL2 R1 125 S_CLOCK TL2 Zo = 50 Ohm C15 0.1u R7 24 VCC C16 10u IN- R3 125 XTAL_SEL TL1 Zo = 50 Ohm C11 0.01u C14 0.1u IN+ C2 C1 S_LOAD R2 84 S_DATA VCC REF_IN X1 |
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