 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DP8473N Datasheet(PDF) 9 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
DP8473N Datasheet(HTML) 9 Page - National Semiconductor (TI) |
|
|
9 / 28 page  Functional Description (Continued) Data Rate Register and Clock Logic This is a two bit register that controls the data rate that the controller uses See Register Description This register feeds logic that se- lects the data rates by programming a prescaler that divides the crystal or clock input by either 3 5 or 6 This causes either 4 MHz 48 MHz and 8 MHz to be input as the master clock for the controller core If the Drive Type pin is high and a 300 kbs data rate is chosen 48 MHz is used to generate 300 kbs but when the DRVTYP pin is low and 300 kbs is selected 4 MHz is used and the actual data rate is 250 kbs See Table VI Low Power Mode Logic This logic is an enhancement over the standard XT AT PS2 design In the Low Power Mode the crystal oscillator controller and all linear circuitry are turned off When the oscillator is turned off the control- ler will typically draw about 1 mA The internal circuitry is disabled while the oscillator is off because the internal cir- cuitry is driven from this clock The oscillator will turn back on automatically after it detects a read or a write to the Main Status or Data Registers It may take a few milli-seconds for the oscillator to stabilize and the mP will be prevented from trying to access the Data Register during this time through the normal Main Status Register protocol (The Request for Master bit in the Main Status Register will be inactive) There are two ways to go into the low power mode One is to command the controller to switch to low power immedi- ately The other method is to set the controller to automati- cally go into the low power mode 500 ms after the beginning of the idle state (based on a 500 kbs (MFM) data rate) This would be invisible to the software The low power mode is programmed through the Mode Command The Data Rate Register and the Drive Control Register are unaffected by the power down mode They will remain ac- tive It is up to the user to ensure that the Motor and Drive select signal are turned off TABLE V Truth Table for Drive Control Register D7 D6 D5 D4 D1 D0 Function X X X 1 0 0 Drive 0 Selected (DR0 e 0) X X1X0 1 Drive 1 Selected (DR1 e 0) X 1 X X 1 0 Drive 2 Selected (DR2 e 0) 1 X X X 1 1 Drive 3 Selected (DR3 e 0) Crystal Oscillator The DP8473 is clocked by a single 24 MHz signal An on-chip oscillator is provided to enable the attachment of a crystal or a clock If a crystal is used a 24 MHz fundamental mode parallel resonant crystal should be used This crystal should be specified to have less than 40X series resistance and shunt capacitance of less than 7 pF Low profile and surface mount crystals should be avoided due to their high start-up resistance which could prohibit the circuit from oscillating If an external oscillator circuit is used it must have a duty cycle of at least 40 – 60% and minimum input levels of 24V and 04V The controller should be configured so that the clock is input into the OSC2 pin and OSC1 is tied to ground Crystals NEL Frequency Controls NEL-54024-2 NEL-C2800N SaRonix SRX 3164 Register Description This section describes the register bits for all the registers that are directly accessible to the mP Table IV (previous page) shows the memory map for these registers Note that in the PC some of the registers are partially decoded this is not the case here All registers occupy only their document- ed addresses MAIN STATUS REGISTER (Read Only) The read only Main Status Register indicates the current status of the disk controller The Main Status Register is always available to be read One of its functions is to control the flow of data to and from the Data Register The Main Status Register indicates when the disk controller is ready to send or receive data It should be read before each byte is transferred to or from the Data Register except during a DMA transfer No delay is required when reading this regis- ter after a data transfer D7 Request for Master Indicates that the Data Register is ready to send or receive data from the mP This bit is cleared immediately after a byte transfer and will become set again as soon as the disk controller is ready for the next byte D6 Data Direction Indicates whether the controller is ex- pecting a byte to be written to (0) or read from (1) the Data Register D5 Non-DMA Execution Bit is set only during the Execu- tion Phase of a command if it is in the non-DMA mode In other words if this bit is set the multiple byte data transfer (in the Execution Phase) must be monitored by the mP ei- ther through interrupts or software polling as described in the Processor Software Interface section D4 Command in Progress Bit is set after the first byte of the Command Phase is written Bit is cleared after the last byte of the Result Phase is read If there is no result phase in a command the bit is cleared after the last byte of the Command Phase is written D3 Drive 3 Seeking Set after the last byte of the Command Phase of a Seek or Recalibrate command is issued for drive 3 Cleared after reading the first byte in the Result Phase of the Sense Interrupt Command for this drive D2 Drive 2 Seeking Same as above for drive 2 D1 Drive 1 Seeking Same as above for drive 1 D0 Drive 0 Seeking Same as above for drive 0 DATA REGISTER (ReadWrite) This is the location through which all commands data and status flow between the CPU and the DP8473 During the Command Phase the mP loads the controller’s commands into this register based on the Status Register Request for Master and Data Direction bits The Result Phase transfers the Status Registers and header information to the mPinthe same fashion 9 |
Similar Part No. - DP8473N |
|
Similar Description - DP8473N |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
