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844441DMI-75LFT Datasheet(PDF) 9 Page - Integrated Device Technology |
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844441DMI-75LFT Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 15 page 9 ©2016 Integrated Device Technology, Inc. Revison E, November 2, 2016 844441 Datasheet Schematic Example Figures 3A and 3B are example 844441 application schematics for either the 8 pin M package or the 16 pin G package. The schematic examples focus on functional connections and are not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In this example, the device is operated at VDD = 2.5V. A 12pF parallel resonant 25MHz crystal is used with tuning capacitors C1 = C2 =14pF, which are recommended for frequency accuracy. Depending on the variation of the parasitic stray capacity of the printed circuit board traces between the crystal and the Xtal_In and Xtal_Out pins, the values of C1 and C2 might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used, but this will require adjusting C1 and C2. In circuit board design, return the capacitors to ground through a single point contact close to the package. Two examples of terminations for LVDS receivers without built-in termination are shown in this schematic. In order to achieve the best possible filtering, it is recommended that the placement of the power filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. Figure 3A. 844441 Schematic Example U1 XTA L_OU T 1 XTA L_I N 2 SS C _SE L0 3 SS C _SE L1 4 GN D 8 nQ 7 Q 6 VD D 5 + - C3 0. 1uF Zo = 50 O hm R1 100 Zo = 50 O hm VD D Zo = 50 O hm C5 0. 1u F Zo = 50 O hm + - 2. 5V R3 50 C6 10uF FB1 BLM18 BB221S N 1 1 2 nQ Pl ace th e 0.1 uF by pas s c ap di rec tly a dja cen t to the V DD pin . Set Logic Input to '0' To Logic Input pins Set Logic Input to '1' Logic Input Pin Examples To Logic Input pins SSC _SEL0 Q SSC _SEL1 Alternate LVDS Termination RU2 Not Install RU 1 1K RD 1 Not Ins t all RD2 1K VD D VD D C2 14pF C1 14pF X1 1 3 2 4 2 5MH z( 12p f) R20 0 XT AL_ IN XTA L_OU T R4 50 C9 0. 1u F nQ Q FOX 603-25-173 crystal |
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