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DRA710 Datasheet(PDF) 3 Page - Texas Instruments |
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DRA710 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 440 page (1x C66x Co-Processor) Mailbox x13 EDMA High-Speed Interconnect Program/Data Storage Connectivity Display Subsystem System (1x ARM Cortex–A15) IVA HD 1080p Video Co-Processor DSP PCIe SS x2 MediaLB (NAND/NOR/ Async) (1x SGX544 3D) VIP x1 (Dual Cortex–M4) intro-001 GPMC / ELM 256-KB ROM OCMC DRA71x GPU MPU IPU1 Serial Interfaces I2C x6 UART x10 McSPI x4 DCAN x2 Spinlock GPIO x8 Timers x16 WDT QSPI EMIF x1 1x 32-bit DDR3/DDR3L sDMA VPE McASP x8 MMU x2 CAL CSI2 x1 BB2D (GC320 2D) (Dual Cortex–M4) IPU2 LCD2 LCD3 HDMI 1.4a 1x GFX Pipeline 3x Video Pipeline Blend / Scale PWM SS x3 HDQ KBD GMAC AVB MOST150 1x USB 3.0 Dual Mode FS/HS/SS w/ PHY 2x USB 2.0 Dual Mode FS/HS 1x PHY, 1x ULPI Radio Accelerators VCP x2 HD ATL 512-KB RAM with ECC DMM MMC / SD x4 PRU-ICSS x2 Copyright © 2016, Texas Instruments Incorporated 3 DRA710, DRA712 DRA714, DRA716, DRA718 www.ti.com SPRS960B – JUNE 2016 – REVISED FEBRUARY 2017 Submit Documentation Feedback Product Folder Links: DRA710 DRA712 DRA714 DRA716 DRA718 Device Overview Copyright © 2016–2017, Texas Instruments Incorporated 1.4 Functional Block Diagram Figure 6-1 is functional block diagram for the device. Figure 1-1. DRA71x Block Diagram |
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