f − Frequency − MHz

45.0

47.5

50.0

52.5

55.0

25

50

75

100

125

150

175

200

G004

Load: CLKOUT = 12 pF || 500 W,

Yn = 25 pF || 500 W

f − Frequency − MHz

0

100

200

300

400

500

25

50

75

100

125

150

175

200

G005

Typical Values @ 3.3 V,

f − Frequency − MHz

−150

−100

−50

0

50

100

150

0

50

100

150

200

G003

Load: CLKOUT = 21 pF || 500 W,

Yn = 25 pF || 500 W

f − Frequency − MHz

0

100

200

300

400

500

25

50

75

100

125

150

175

200

G002

Load: CLKOUT = 12 pF || 500 W,

6

CDCVF2505

SCAS640G – JULY 2000 – REVISED AUGUST 2016

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Product Folder Links: CDCVF2505

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Copyright © 2000–2016, Texas Instruments Incorporated

(1)

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be

obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for

propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not

apply for input modulation under SSC application.

(2)

(3)

7.7 Switching Characteristics

(1)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Propagation delay, normalized

(see Figure 2)

CLKIN to Yn, f = 66 MHz to 200 MHz

–150

150

ps

Yn to Yn

150

ps

Jitter (cycle-to-cycle)

(see Figure 4)

f = 66 MHz to 200 MHz

70

150

ps

f = 24 MHz to 50 MHz

200

400

odc

Output duty cycle

(see Figure 3)

45%

55%

Rise time

0.5

2

ns

Fall time

0.5

2

ns

7.8 Typical Characteristics

at 3.3 V, 25°C (unless otherwise noted)

vs Frequency (Tuned for Minimum Delay)

Figure 3. Duty Cycle vs Frequency

Figure 4. Cycle-Cycle Jitter vs Frequency