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DRA725AGGABCQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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DRA725AGGABCQ1 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 408 page  4 DRA722, DRA724, DRA725, DRA726 SPRS956B – MARCH 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: DRA722 DRA724 DRA725 DRA726 Table of Contents Copyright © 2016–2017, Texas Instruments Incorporated Table of Contents 1 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 2 1.3 Description ............................................ 2 1.4 Functional Block Diagram ........................... 3 2 Revision History ......................................... 5 3 Device Comparison ..................................... 6 3.1 Device Comparison Table ............................ 6 4 Terminal Configuration and Functions .............. 8 4.1 Terminal Assignment ................................. 8 4.2 Ball Characteristics ................................... 9 4.3 Multiplexing Characteristics ......................... 71 4.4 Signal Descriptions .................................. 88 5 Specifications ......................................... 126 5.1 Absolute Maximum Ratings ........................ 126 5.2 ESD Ratings ....................................... 127 5.3 Power on Hour (POH) Limits ...................... 127 5.4 Recommended Operating Conditions ............. 128 5.5 Operating Performance Points ..................... 131 5.6 Power Consumption Summary .................... 153 5.7 Electrical Characteristics ........................... 153 5.8 Thermal Characteristics ............................ 162 5.9 Power Supply Sequences ......................... 163 6 Clock Specifications ................................. 174 6.1 Input Clock Specifications ......................... 175 6.2 DPLLs, DLLs Specifications ....................... 184 7 Timing Requirements and Switching Characteristics ........................................ 188 7.1 Timing Test Conditions ............................ 188 7.2 Interface Clock Specifications ..................... 188 7.3 Timing Parameters and Information ............... 188 7.4 Recommended Clock and Control Signal Transition Behavior ............................................ 190 7.5 Virtual and Manual I/O Timing Modes ............. 190 7.6 Video Input Ports (VIP) ............................ 192 7.7 Display Subsystem - Video Output Ports .......... 211 7.8 Display Subsystem - High-Definition Multimedia Interface (HDMI) ................................... 221 7.9 Camera Serial Interface 2 CAL bridge (CSI2) ..... 222 7.10 External Memory Interface (EMIF) ................. 222 7.11 General-Purpose Memory Controller (GPMC) ..... 222 7.12 Timers .............................................. 246 7.13 Inter-Integrated Circuit Interface (I2C) ............. 246 7.14 HDQ / 1-Wire Interface (HDQ1W) ................. 249 7.15 Universal Asynchronous Receiver Transmitter (UART) ............................................. 252 7.16 Multichannel Serial Peripheral Interface (McSPI) . 253 7.17 Quad Serial Peripheral Interface (QSPI) .......... 259 7.18 Multichannel Audio Serial Port (McASP) .......... 263 7.19 Universal Serial Bus (USB) ........................ 283 7.20 Serial Advanced Technology Attachment (SATA) . 284 7.21 Peripheral Component Interconnect Express (PCIe) .............................................. 285 7.22 Controller Area Network Interface (DCAN) ........ 285 7.23 Ethernet Interface (GMAC_SW) ................... 286 7.24 Media Local Bus (MLB) interface .................. 299 7.25 eMMC/SD/SDIO ................................... 300 7.26 General-Purpose Interface (GPIO) ................ 324 7.27 Audio Tracking Logic (ATL) ........................ 325 7.28 System and Miscellaneous interfaces ............. 325 7.29 Test Interfaces ..................................... 325 8 Applications, Implementation, and Layout ...... 330 8.1 Introduction ........................................ 330 8.2 Power Optimizations ............................... 331 8.3 Core Power Domains .............................. 342 8.4 Single-Ended Interfaces ........................... 352 8.5 Differential Interfaces .............................. 354 8.6 Clock Routing Guidelines .......................... 375 8.7 DDR3 Board Design and Layout Guidelines ....... 376 9 Device and Documentation Support .............. 400 9.1 Device Nomenclature .............................. 400 9.2 Tools and Software ................................ 402 9.3 Documentation Support ............................ 402 9.4 Receiving Notification of Documentation Updates . 403 9.5 Community Resources ............................. 403 9.6 Related Links ...................................... 403 9.7 Trademarks ........................................ 403 9.8 Electrostatic Discharge Caution ................... 404 9.9 Export Control Notice .............................. 404 9.10 Glossary ............................................ 404 10 Mechanical Packaging and Orderable Information ............................................. 405 |
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