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MAP3613SIRH Datasheet(PDF) 2 Page - MagnaChip Semiconductor. |
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MAP3613SIRH Datasheet(HTML) 2 Page - MagnaChip Semiconductor. |
2 / 16 page Confidential Datasheet Version 1.0 Mar 28 th 2016 2 Pin Configuration PGND1 1 2 GATE1 3 GND 4 VCC 5 6 ADIM 20 FLT 19 PWM1 18 PWM2 17 MODE 16 SEL 15 MAP3613 CS1 TOFF 7 NC 14 8 13 PWM3 9 10 GATE3 12 CS3 11 GATE2 CS2 PGND3 PGND2 SOIC-20L Pin Description 24leads SOIC Name Description 1 PGND1 Power GND for CH1 2 CS1 External current sense for CH1(Note 1) 3 GATE1 GATE driver output to drive external NMOSFET for CH1 4 GND Ground 5 VCC Power supply input. Need external bypass capacitor 6 TOFF Setting for GATE off-time(Note 2) 7 NC No Connection (Note 3) 8 GATE2 GATE driver output to drive external NMOSFET for CH2 9 CS2 External current sense for CH2(Note 1) 10 PGND2 Power GND for CH2 11 PGND3 Power GND for CH3 12 CS3 External current sense for CH3(Note 1) 13 GATE3 GATE driver output to drive external NMOSFET for CH3 14 SEL Logic input for selecting OD1 or OD2 protection. Default logic ‘Low’ (Note 4) 15 MODE Enable logic input for Over-Duty protection. Default logic ‘Low’ (Note 5) 16 PWM3 PWM signal input for CH3 17 PWM2 PWM signal input for CH2 18 PWM1 PWM signal input for CH1 19 FLT Fault Output 20 ADIM Setting for LED current thru external DC voltage Note 1: Connect external resistor to PGNDx to sense the external power MOSFETx source current as shown in typical application Note 2: Connect external resistor to GND to set GATE off-time as shown in typical application Note 3: Must be connected to GND externally. Note 4: Logic ‘H’ OD1 protection, Logic ‘L’ or floating OD2 protection Note 5: Logic ‘H’ ODP disable, Logic ‘L’ or floating ODP enable |
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