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AS4C128M8D3L-12BIN Datasheet(PDF) 5 Page - Alliance Semiconductor Corporation |
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AS4C128M8D3L-12BIN Datasheet(HTML) 5 Page - Alliance Semiconductor Corporation |
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5 / 88 page  1Gb DDR3L – AS4C128M8D3L Confidential 5 Rev. 2.0 Aug. /2014 Figure 3. State Diagram This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail. Power On Automatic Sequence Command Sequence Power applied Reset Procedure Initialization RESET from any state ZQCL ZQ Calibration Idle Self Refresh Refreshing MRS REF ZQCL,ZQCS Active Power Down Activating Precharge Power Down ACT Bank Activating Writing Writing Reading Precharging PD X PD E RE AD READ READ A RE AD A WRITE READ WRITE REA D A WR ITE A WRITE A ACT = Active PRE = Precharge REF = Refresh PREA = Precharge All MRS = Mode Register Set ZQCL = ZQ Calibration Long Read = RD, RDS4, RDS8 Read A = RDA, RDAS4, RDAS8 Write = WR, WRS4, WRS8 Write A = WRA, WRAS4, WRAS8 RESET = Start RESET Procedure ZQCS = ZQ Calibration Short PDE = Enter Power-down PDX = Exit Power-down SRE = Self-Refresh entry SRX = Self-Refresh exit MPR = Multi-Purpose Register Reading MRS,MPR, Write Leveling |
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