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AS4C128M16D3-12BAN Datasheet(PDF) 11 Page - Alliance Semiconductor Corporation |
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AS4C128M16D3-12BAN Datasheet(HTML) 11 Page - Alliance Semiconductor Corporation |
11 / 83 page l Reset Procedure at Stable Power The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns). 2. Follow Power-up Initialization Sequence step 2 to 11. 3. The Reset sequence is now completed. DDR3 SDRAM is ready for normal operation. Figure 5. Reset Procedure at Power Stable Condition CK# VDDQ Tb Tc Td Te Tf Tg Th Ti Tj Ta RESET# CK tCKSRX Tk T=100ns T=500µs tDLLK tXPR tMRD tMRD tMRD tMOD tZQinit MRS Note 1 MRS MRS MRS ZQCL Note 1 VALID MR3 MR2 MR1 MR0 VALID VALID VDD COMMAND CKE BA ODT RTT tIS tIS tIS tIS Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW Don't Care TIME BREAK NOTE 1. From time point “Td”until “Tk”NOP or DES commands must be applied between MRS and ZQCL commands. Tmin=10ns 2Gb Auto-AS4C128M16D3 Confidential -11/83- Rev.1.0 June 2015 |
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