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I960 Datasheet(PDF) 10 Page - Intel Corporation |
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I960 Datasheet(HTML) 10 Page - Intel Corporation |
10 / 70 page 4 ADVANCE INFORMATION i960® Rx I/O Processor at 3.3 V 2.1.9 Secondary PCI Arbitration Unit The Secondary PCI Arbitration Unit provides PCI arbitration for the secondary PCI bus. It includes a fairness algorithm with programmable priorities and six PCI Request and Grant signal pairs. This arbitra- tion unit can also be disabled to allow for external arbitration. 2.2 i960 Core Features (80960JF) The processing power of the 80960Rx comes from the 80960JF processor core. The 80960JF is a new, scalar implementation of the 80960 Core Architec- ture. Figure 2 shows a block diagram of the 80960JF Core processor. Factors that contribute to the 80960 family core’s performance include: • Single-clock execution of most instructions • Independent Multiply/Divide Unit • Efficient instruction pipeline minimizes pipeline break latency • Register and resource scoreboarding allow overlapped instruction execution • 128-bit register bus speeds local register caching • 4 Kbyte two-way set-associative, integrated instruction cache • 2 Kbyte direct-mapped, integrated data cache • 1 Kbyte integrated data RAM delivers zero wait state program data The 80960 core operates out of its own 32-bit address space, which is independent of the PCI address space. The local bus memory can be: • Made visible to the PCI address space • Kept private to the 80960 core • Allocated as a combination of the two Figure 2. 80960JF Core Block Diagram Programmable Bus Control Unit Interrupt Controller Control Address/ Instruction Sequencer Physical Region Configuration Interrupt Port 1Kbyte Data RAM Memory Interface Execution Multiply Unit Divide Unit Memory-Mapped Register Interface Data Bus Global / Local Register File SRC2 DST SRC1 Address Control Effective Constants Generation Unit Address 32-bit Addr 32-bit Data Bus Request Queues and Two 32-Bit Timers 8-Set Local Register PLL, Clocks, Power Mgmt Boundary Scan Controller TAP 5 128 9 32 32-bit buses address / data 3 Independent 32-Bit SRC1, SRC2, and DST Buses Instruction Cache 4 Kbyte Two-Way Set Associative 2Kbyte Direct Mapped Data Cache S_CLK Cache |
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