843442AG REVISION B 08/21/2015

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©2015 Integrated Device Technology, Inc.

843442 Data Sheet

FEMTOCLOCK™ SAS/SATA Clock Generator

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 4.

Figure 4. LVPECL Driver Circuit and Termination

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Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

[(2V – 0.9V)/50

] * 0.9V = 19.8mW

[(2V – 1.7V)/50

] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

V

OUT

V

CC

V

Q1

RL

50

Ω