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AS4C32M16MD1 Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation |
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AS4C32M16MD1 Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation |
4 / 75 page AS4C32M16MD1 Confidential 4 Rev. 2.0/February 2014 2. GENERAL DESCRIPTION This device is 536,870,912 bits of double data rate synchronous DRAM organized as 4 banks of 8,388,608 words by 16 bits. The synchronous operation with Data Strobe allows extremely high performance. JSC is applied to reduce leakage and refresh currents while achieving very high speed. I/O transactions are possible on both edges of the clock. The ranges of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Table 1. Speed Grade Information Speed Grade – Data rate Clock Frequency CAS Latency tRCD (ns) tRP (ns) 400Mbps (max) 200 MHz (max) 3 15 15 Table 2 – Ordering Information for ROHS Compliant Products Product part No Org Temperature Max Clock (MHz) Package AS4C32M16MD1-5BCN 32 x 16 -30°C to 85°C 200 60-ball FBGA |
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