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AS4C32M16SM-7TIN Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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AS4C32M16SM-7TIN Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
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2 / 73 page  AS4C32M16SM Confidential 2 | P a g e R e v 1 . 0 , J u l y 2014 512M (32M x 16) bit Synchronous DRAM (SDRAM) Confidential Preliminary (Rev. 1.0, July /2014) Features PC133-compliant Configurations – 32 Meg x 16 (8 Meg x 16 x 4 banks) Fully synchronous; all signals registered on positive edge of system clock Internal, pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto precharge, includes concurrent auto precharge and auto refresh modes Self refresh mode Auto refresh–64ms, 8192-cycle refresh (commercial and industrial) LVTTL-compatible inputs and outputs Single 3.3V ±0.3V power supply Operating temperature range o Commercial (0˚C to +70˚C) o Industrial (–40˚C to +85˚C) Timing – cycle time o 7.5ns @ CL = 3 (PC133) o 7.5ns @ CL = 2 (PC133) Plastic package – OCPL2 o 54-pin TSOP II (400 mil) Pb-free All parts ROHS Compliant Table 1. Key Timing Parameters Clock Frequency Set up time Hold time Access time CL =3 tRCD (ns) tRP (ns) 133 MHz 1.5ns 0.8ns 5.4ns 13.75 13.75 CL = CAS (READ) latency Table 2 – Ordering Information Product part No Org Temperature Package AS4C32M16SM-7TCN 32M x 16 Commercial 0°C to 70°C 54-pin TSOP II (400mil) AS4C32M16SM-7TIN 32M x 16 Industrial -40°C to 85°C 54-pin TSOP II (400mil) Table 3 – Address Table Parameter 32M x 16 Configuration 8 Meg x 16 x 4 banks Refresh Count 8K Row Addressing 8K A [12:0] Bank Addressing 4 BA [1:0] Column Addressing 1K A [9:0] |
Similar Part No. - AS4C32M16SM-7TIN |
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Similar Description - AS4C32M16SM-7TIN |
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