Data Strobe and Data Mask

Operation at Burst Reads

The Data Strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. The data

strobe signal goes 1 clock cycle low before data is driven by the mobile DDR and then toggles low to high and high to low

till the end of the burst. CAS latency is specified to the first low to high transition. The edges of the Output Data signals

and the edges of the data strobe signals during a read are nominally coincident with edges of the input clock.

The tolerance of these edges is specified by the parameters tAC and tDQSCK and is referenced to the crossing point of

the CLK and /CLK signal. The tDQSQ timing parameter describes the skew between the data strobe edge and the output

data edge.

The following table summarizes the mapping of LDQS, UDQS(DQS0 ~ DQS3) and LDM, UDM(DM0 ~ DM3) signals to

the data bus.

Mapping of DQS0~DQS3 and DM0~DM3

The minimum time during which the output data is valid is critical for the receiving device. This also applies to the Data

Strobe DQS during a read since it is tightly coupled to the output data. The parameters tQH and tDQSQ define the mini-

mum output data valid window. Prior to a burst of read data, given that the device is not currently in burst read mode,

the data strobe signals transit from Hi-Z to a valid logic low. This is referred to as the data strobe “read preamble” tRPRE.

This transition happens one clock prior to the first edge of valid data.

Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe sig-

nals transit from a valid logic low to Hi-Z. This is referred to as the data strobe “read postamble” tRPST.

Data strobe signal

Data mask signal

Controlled data bus

LDQS, DQS0

LDM, DM0

DQ7 .. DQ0

UDQS, DQS1

UDM, DM1

DQ8 .. DQ15

DQS2

DM2

DQ16 .. DQ23

DQS3

DM3

DQ24 .. DQ31

 

 

 

 

AS4C32M32MD1

Confidential

-9-

Rev.1.0 Sep.2014