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AS4C128M8D1-6TIN Datasheet(PDF) 7 Page - Alliance Semiconductor Corporation |
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AS4C128M8D1-6TIN Datasheet(HTML) 7 Page - Alliance Semiconductor Corporation |
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7 / 57 page  Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock cycles are required to meet tMRD spec. The mode register contents can be changed using the same com- mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg- ister is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a ProMOS specific test mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. 1. MRS can be issued only at all banks precharge state. 2. Minimum tRP is required to issue MRS command. Address Bus CAS Latency A6 A5 A4 Latency 0 0 0 Reserve 0 0 1 Reserve 01 0 2 01 1 3 1 0 0 Reserve Reserve 10 1 1 1 0 2.5 1 1 1 Reserve Burst Length A2 A1 A0 Latency Sequential Interleave 0 0 0 Reserve Reserve 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 Reserve Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve Reserve 1 1 1 Reserve Reserve A 7 mode 0 Normal 1 Test A3 Burst Type 0 Sequential 1 Interleave * RFU(Reserved for future use) should stay "0" during MRS cycle. A8 DLL Reset 0No 1 Yes Mode Register Set 0 RFU : Must be set "0" Extended Mode Register Mode Register DLL I/O A0 DLL Enable 0 Enable 1 Disable A1 I/O Strength 0 Full 1 Half BA0 An ~ A0 0 (Existing)MRS Cycle 1 Extended Funtions(EMRS) Command 2 01 5 34 8 67 CK, CK tCK tMRD Precharge All Banks Mode Register Set tRP*2 *1 Any Command BA1 BA 0 A3 A2 A1 A0 0TM CAS Latency BT Burst Length RFU DLL MRS MRS A12 to 0 Confidential - 7 of 57 - Rev. 1.0 Dec. 2016 AS4C128M8D1-6TIN |
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