IDT8P79818NLGI datasheet(1/34 Pages) IDT

Part #	IDT8P79818NLGI

Description	Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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December 19, 2016

Description

The device is intended to take 1 or 2 reference clocks, select

between them, using a pin or register selection and generate up to 8

outputs that may be the same as the reference frequency or

integer-divider versions of it.

The 8P79818 supports two output banks, each with its own divider

and power supply. All outputs in one bank would generate the same

output frequency, but each output can be individually controlled for

output type, output enable or even powered-off.

The device supports a serial port for configuration of the parameters

while in operation. The serial port can be selected to use the I2C or

SPI protocol. After power-up, all outputs will come up in LVDS mode

and may be programmed to other configurations over the serial port.

Outputs may be enabled or disabled under control of the OE input

pin.

The device can operate over the -40°C to +85°C temperature range.

Features

▪ Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS

reference clocks

— Accepts input frequencies ranging from 1PPS (1Hz) to

700MHz

▪ Select which of the two input clocks is to be used as the reference

clock for which divider via pin or register selection

— Switchover will not generate any runt clock pulses on the

output

▪ Generates eight differential outputs

or eight LVCMOS outputs, Bank A only

— Differential outputs selectable as LVPECL, LVDS, CML or

HCSL

— Differential outputs support frequencies from 1PPS to 700MHz

— LVCMOS outputs support frequencies from 1PPS to 200MHz

— LVCMOS outputs in the same pair may be inverted or in-phase

relative to one another

▪ Outputs arranged in 2 banks of 4 outputs each

— Each bank supports a separate power supply of 3.3V, 2.5V or

1.8V

— 1.5V output voltage is also supported for LVCMOS, Bank A

only

— One divider per output bank, supporting divide ratios of 2...511

or divider bypass

▪ Output enable control pin

— Output enable or disable will not cause any runt pulses

▪ Register programmable via I2C / SPI serial port

— Individual output enables, output type selection and output

power-down control bits supported

— Input mux selection control bit

▪ Core voltage supply of 3.3V, 2.5V or 1.8V

▪ -40°C to +85°C ambient operating temperature

▪ Lead-free (RoHS 6) packaging

8P79818

Datasheet

Programmable Low Additive Jitter 2:8

Buffer with Dividers and Universal Outputs

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