AS4C512M32MD3-15BCN datasheet(2/104 Pages) ALSC

Part #	AS4C512M32MD3-15BCN

Description	Operating case temperature range

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Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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HIGH PERFORMANCE 16Gbit LPDDR3 SDRAM

8 BANKS X 32Mbit X 32 X 2 CS

Specifications

-

Density : 16G bits

-

Organization :

- 32M words x 32 bits x 8 banks x 2 CS

-

Package :

- 178-ball FBGA

- Lead-free (RoHS compliant) and Halogen-free

-

Power supply :

- VDD1 = 1.8V (1.7V~1.95V)

- VDD2/VDDQ/VDDCA = 1.2V (1.14V~1.3V)

-

HSUL_12 interface (High Speed Unterminated Logic

1.2V)

-

Data rate :

- 1333Mbps RL=10

-

RL / WL select setA / setB

-

Driver strength :

- Typical : 34.3/40/48/60/80

Ω

- PD34.3_PU40 / PD40_PU48 / PD34.3_PU48

-

ODT: RZQ/4, RZQ/2, RZQ/1 (RZQ = 240

Ω)

-

Operating case temperature range

- Com

mercial Tc = -25°C to +85°C

Features

-

Low power consumption

-

Eight-bit prefetch DDR architecture and BL8 only

-

Eight internal banks for concurrent operation

-

Double data rate architecture for command, address

and data Bus

-

Bidirectional and differential data strobe per byte of

data (DQS and DQS)

-

DQS is edge-aligned with data for READs, center-

aligned with data for WRITEs

-

Differential clock inputs (CK and CK)

-

Data mask (DM) for write data

-

Programmable READ and WRITE latencies (RL/WL)

-

Auto Refresh and Self Refresh

-

Per-bank refresh for concurrent operation

-

Partial-array self refresh (PASR)

-

On-chip temperature sensor to control self refresh rate

for temperature compensated self refresh (TCSR)

-

Deep power-down mode (DPD)

-

Selectable output drive strength (DS)

-

Selectable On-Die Termination

-

CA Training

-

Write leveling via MR setting

-

Clock stop capability

-

DQ calibration offering specific DQ output patterns

-

ZQ calibration

Table1.OrderingInformation

Product part No

Org

Temperature

Max Clock (MHz)

512M x 32

667

Package

178-ball FBGA

Table2.SpeedGradeInformation

Speed Grade

Clock Frequency

Read latency (RL) Write Latency (Set A) Clock Cycle Time (tCK)

DDR3L-1333

667 MHz

10

6

1.5

AS4C512M32MD3-15BCN

Commercial -25°C to +85°C

AS4C512M32MD3-15BCN

Confidential

- 2 of 104 -

Rev.1.0 Nov. 2016

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AS4C512M32MD3-15BCN Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation

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