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KESRX04IG Datasheet(PDF) 8 Page - Zarlink Semiconductor Inc |
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KESRX04IG Datasheet(HTML) 8 Page - Zarlink Semiconductor Inc |
8 / 21 page 8 KESRX04 IF amp/RSSI detector This is a log amplifier with a gain > 80dB and an RSSI output used as the detector. The 3dB bandwidth of the IF log amplifier is typically 20MHz to allow for high IF’s to be used. However, normally, this wide IF bandwidth would limit the overall sensitivity of the receiver due to the amplified wide band noise generated in the first IF stage. The RSSI detector is not frequency selective so that any wide band noise introduced after the intermediate filter will be detected as signal. A simple LC noise reduction filter is therefore positioned part way down the log amplifier to reduce the noise power from the earlier stages. Typically this filter only needs to be a fixed component parallel LC filter (L5 // C7) between pins IFFLT1 and IFFLT2 with a 1MHz bandwidth (i.e. Q~10). There is an internal 20Kohm damping resistor across these pins which will determine the Q and the choice of L and C values. i.e. L fQ = 20000 2. . IF π . ; C Q fIF = 2 20000 .. . π An external damping resistor should not be used as this will alter the gain of the log amplifier. A ceramic resonator or filter is not a suitable component here as a low impedance dc path must be maintained to remove dc voltage offsets in the high gain log amplifier. Further improvement in sensitivity can be gained by using a narrow band IF ceramic filter and a narrower noise reduction filter. For a low IF receiver, <1MHz, a low pass filter can be used for both the IF and noise reduction filters. Such a receiver however will have virtually no image rejection capability, and will thus have a 3dB penality in noise factor impairing the ultimate sensitivity of the receiver by a minimum of 3dB. The RSSI output transfer characteristic, at pin RSSI, has a slope of about 16mV/dB. A typical transfer characteristic from RF in input to RSSI output is plotted in Figure 9B, measured with a constant RF input signal. This shows the effect of the AGC in extending the range of the detector to +10dBm RF input signal and includes the effect of the AGC circuit adapting to this signal level. Because the RF amplifier AGC has a fast attack time - slow decay time characteristic the gain of the stage remains con- stant during the data burst. This means that the change in output for a given extinction ratio also remains constant at approximately 16mV/dB up to peak input signal levels >+10dBm. This requires the decay time constant to exceed the transmit- ted bit period and no long period of zero signal power has been transmitted. Increasing the decay time constant of the AGC circuit by increasing the value of C8 will impair the settling time (time to good data) of the receiver. When duty cycling the operation to the receiver between PD0 and PD2 to lower power consumption of the receiver. When Duty cycling the receiver between PD1 and PD2 the settling time of the receiver is independent of C8. In the application circuit Figure 11 the value of C8 is configured for minimum settling time. Anti-jamming Circuit The output of the RSSI is AC coupled into the Anti-jamming circuit where the signal is DC restored on the peak signal level Figure 7. The coupling capacitor charges to the appropriate DC level which is related to the final slice level for the data comparator. The anti-jamming circuit amplifies the peak of the signal to recover the data signal component even in the presence of CW jamming signals. The interferer causes modulation of the wanted signal at the beat frequency of the two signals and reduces the amplitude of the wanted data component making it more difficult to recover. By-passing the anti-jam circuit Figure 8 will result in data corruption for interfering RF signal levels 6dB below the wanted signal (Figure 5A) The DC restoration circuit has a fast attack time and slow decay time, both controlled by the value of coupling capacitor chosen between RSSI and DETB pins. Figure 5 illustrates a suitable test setup for characterising the interference rejection and selectivity of the receiver. Figure 5A illustrates the in-band interference rejection with the anti-jam circuit connected Figure 7 and by-passed(Figure 8) at 3V Tamb = 25 °C. Note, the improvement in interference rejection between the two modes of operation over the wanted signal range of -94 to -20dBm. Figure 5B illustrates the difference in receiver selectivity with the ant-jam circuit connected (Figure 7) and by-passed (Figure 8). Note, the improvement in receiver selectivity between the two modes of operation. The selectivity curve with the anti- jam circuit by-passed is governed by the response of the front end SAW filter, IF ceramic filter and data filter. Providing no rejection for interfering signals within the pass band of the receiver. Whereas the receiver with the anti-jam circuit connected actively responds to the presence of the in-band interfering signal to recover the wanted OOK modulated signal. The action of the anti-jam circuit centres the bandwidth of the receiver around the wanted signal proportional to the data filter bandwidth to suppress the interfering beat frequency. Figures 5A and 5B were recorded with the following component specification. Component Specification (Figure 7) Anti-Jam removed (Figure 8) R6 130K Ω R6 12K Ω C2 270pF C2 removed Data Filter BW 5kHz Data Filter BW 5kHz IFBW 470kHz IF BW 470kHz SAW BW 750kHz SAW BW 750kHz OOK modulation 4kB/s (50% duty cycle) OOK modulation 4kB/S (50% duty cycle) Component specification for Figure 5A and 5B |
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