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LMT84DCK-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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LMT84DCK-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 30 page LMT84, LMT84-Q1 SNIS167C – MARCH 2013 – REVISED OCTOBER 2015 www.ti.com 7.7 Electrical Characteristics Unless otherwise noted, these specifications apply for VDD = +1.5V to +5.5V. MIN and MAX limits apply for TA = TJ = TMIN to TMAX ; typical values apply for TA = TJ = 25°C. PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX (1) UNITS Sensor Gain –5.5 mV/°C Source ≤ 50 μA, (VDD - VOUT) ≥ 200 mV -1 –0.22 mV Load Regulation (3) Sink ≤ 50 μA, VOUT ≥ 200 mV 0.26 1 mV Line Regulation (4) 200 μV/V TA = 30°C to 150°C, (VDD - VOUT) ≥ 100 mV 5.4 8.1 μA IS Supply Current TA = -50°C to 150°C, (VDD - VOUT) ≥ 100 mV 5.4 9 μA CL Output Load Capacitance 1100 pF Power-on Time (5) CL= 0 pF to 1100 pF 0.7 1.9 ms Output drive ±50 µA (1) Limits are specific to TI's AOQL (Average Outgoing Quality Level). (2) Typicals are at TJ = TA = 25°C and represent most likely parametric norm. (3) Source currents are flowing out of the LMT84/LMT84-Q1. Sink currents are flowing into the LMT84/LMT84-Q1. (4) Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in Output Voltage Shift. (5) Specified by design and characterization. 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: LMT84 LMT84-Q1 |
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