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IDT5P90005C Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT5P90005C Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 15 page  REVISION C 07/03/14 3 SERIAL REAL-TIME CLOCK IDT5P90005C DATASHEET Device Operation The IDT5P90005C clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1st byte: seconds register 2nd byte: minutes register 3rd byte: century/hours register 4th byte: day register 5th byte: date register 6th byte: month register 7th byte: years register 8th byte: control register The IDT5P90005C clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time, to prevent erroneous data from being written to the device from an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to VCC at VSO and recognizes inputs. |
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