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AS7C316096C Datasheet(PDF) 7 Page - Alliance Semiconductor Corporation |
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AS7C316096C Datasheet(HTML) 7 Page - Alliance Semiconductor Corporation |
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7 / 12 page  AS7C316096C Rev. 1.0 2048K X 8 BIT HIGH SPEED CMOS SRAM Confidential 6 Rev 1.0 / May 2014 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) Dout Data Valid tOH tAA Address tRC Previous Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) Dout Data Valid tOH OE# tACE CE# tAA Address tRC High-Z High-Z tCLZ tOLZ tOE tCHZ tOHZ Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. |
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