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A4411 Datasheet(PDF) 9 Page - Allegro MicroSystems |
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A4411 Datasheet(HTML) 9 Page - Allegro MicroSystems |
9 / 45 page Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V A4411 9 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Characteristic Symbol Test Conditions Min. Typ. Max. Unit OUTPUT VOLTAGE SPECIFICATIONS Buck Output Voltage – Regulating VVREG VVIN = 13.5 V, ENB = 1, 0.1 A < IVREG < 1.25 A 5.25 5.35 5.45 V PULSE-WIDTH MODULATION (PWM) PWM Ramp Offset PWM1OFFS VCOMP1 for 0% duty cycle – 400 – mV LX1 Rising Slew Rate Control [2] LX1RISE VVIN = 13.5 V, 10% to 90%, IVREG = 1 A, RSLEW = 22.1 kΩ – 0.9 – V/ns VVIN = 13.5 V, 10% to 90%, IVREG = 1 A, RSLEW = 249 kΩ – 0.3 – V/ns LX1 Falling Slew Rate [2] LX1FALL VVIN = 13.5 V, 90% to 10%, IVREG = 1 A – 1.5 – V/ns Buck Minimum On-Time tON,MIN,BUCK – 100 150 ns Buck Maximum Duty Cycle DMAX,BUCK tOFF,BUCK < 50 ns – 100 – % Boost Minimum Off-Time tON,MIN,BST 100 130 230 ns Boost Duty Cycle DMIN,BST After VVIN > VINSTART, VVIN = 6.5 V – 20 – % DMAX,BST After VVIN > VINSTART, VVIN = 3.5 V – 58 68 % COMP1 to LX1 Current Gain gmPOWER1 – 4.5 – A/V Slope Compensation [2] SE1 fOSC = 2 MHz 1.04 1.48 1.92 A/µs fOSC = 400 kHz 0.22 0.33 0.44 A/µs INTERNAL MOSFET MOSFET On-Resistance RDSon VVIN = 13.5 V, TJ = ‒40°C [2], IDS = 0.1 A – 50 65 mΩ VVIN = 13.5 V, TJ = 25°C [3], IDS = 0.1 A – 75 90 mΩ VVIN = 13.5 V, TJ = 150°C, IDS = 0.1 A – 150 180 mΩ MOSFET Leakage IFET,LKG IC disabled, VLX1 = 0 V, VVIN = 16 V, −40°C < TJ < 85°C [3] – – 10 µA IC disabled, VLX1 = 0 V, VVIN = 16 V, −40°C < TJ < 150°C – 50 150 µA ERROR AMPLIFIER Open-Loop Voltage Gain AVOL1 – 60 – dB Transconductance gmEA1 VSS1 = 750 mV 550 750 950 µA/V VSS1 = 500 mV 275 375 475 µA/V Output Current IEA1 – ±75 – µA Maximum Output Voltage EA1VO(max) 1.3 1.7 2.1 V Minimum Output Voltage EA1VO(min) – – 300 mV COMP1 Pull-Down Resistance RCOMP1 HICCUP1 = 1 or FAULT1 = 1 or IC disabled, latched until VSS1 < VSS1RST – 1 – kΩ 1 Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 2 Ensured by design and characterization, not production tested. 3 Specifications at 25°C or 85°C are guaranteed by design and characterization, not production tested. ELECTRICAL CHARACTERISTICS (continued) [1]: Valid at 3.5 V < VIN < 36 V, –40°C < TA = TJ < 150°C, unless otherwise specified. Continued on next page... |
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