with 50 V Load Dump and Short-to-Battery Protection

A4481

8

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Place the input and output capacitors as close as possible and on

the same side of the PCB and IC.

Place thermal vias directly under the device in a tight pattern, as

shown in Figure 4, to improve dissipation.

PCB LAYOUT GUIDELINES

Figure 3: A4481 Layout Example

Figure 4: Suggested PCB layout for thermal optimization

(maximum available bottom-layer copper recommended)

Ø0.3 mm via

Top-layer

exposed copper

Signal traces

LJ package

exposed

thermal pad

LJ package

footprint

0.7 mm

0.7 mm

VIN

VIN

NC

ENB

VOUT

GND

GND

POK

1

2

3

4

8

7

6

5

PAD

Ground

Input

Capacitor

Output

Capacitor

PowerOK

Output

µP Enable

V

IN

V

OUT

Tie directly to VIN to

automatically enable

the A4481