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MAS7838 Datasheet(PDF) 4 Page - Micro Analog systems |
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MAS7838 Datasheet(HTML) 4 Page - Micro Analog systems |
4 / 9 page DA7838.002 20 September, 2000 4 (9) (/(&75,&$/ &+$5$&7(5,67,&6 Timings between synchronous clocks and data are shown below. Note that absolute delays depend on the speed of the data transmission. If pin TSL = 1 (Automatic synchronous sampling timing) )81&7,216 u $V\QFKURQRXV WR V\QFKURQRXV FRQYHUWHU The synchronous start-stop character, TDI (transmitter data input), is read into the Tx buffer. When the character is available the data bits are transferred as TDO (transmitter data output) with the synchronous timing signal TXC (transmitter clock). The bit rate of TDI must be the same as the TDO rate within -2.5%...+1% or -2.5%...+2.3% tolerance depending on XESR (extended signalling rate) signal. The transmitter adds extra stop bits to the synchronous data stream, if TDI is slower than TDO. The over speed is handled by deleting one stop bit in every 8th character at maximum in the synchronous output data TDO. When extended signal rate (XESR = 0) is used 4th stop bit may be deleted. When the transmitter detects a break signal( at least M bits of start polarity, where M is length of character), it sends 2M + 3 bits of start - polarity to TDO. If the break is longer than 2M + 3 bits, then all bits are transferred to TDO. After a break signal, at least 2M bits of stop polarity must be transmitted before sending further data. u 6\QFKURQRXV WR DV\QFKURQRXV FRQYHUWHU The synchronous RDI (receiver data input) is buffered to recognise the stop and start bits. If a missing stop bit is detected, it is added to the RDO (receiver data output). In this case the stop bits are shortened 12.5% (25% if XESR = 0) during each character. When the receiver gets at least 2M + 3 bits of start polarity, it does not add stop bits to RDO. This enables the break signal to go through the buffer. uÃ&RQYHUWLQJ ZLWK KLJKHU VSHHG WLPLQJ An alternative method to handle the over speed in asynchronous data is to boost synchronous timing TXC and RXC by 1-2%. In this mode XHST (higher speed timing) = 0. In this case there is no need to delete any stop bits in the transmitter buffer. The break signal goes through unchanged. On the receiver side the synchronous data, RDI, is transferred directly to the asynchronous output RDO with RXC. T RXC T2 T3 RXC RDI TXC TDO T TXC delay T1 |
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