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MAX5580AEUP Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX5580AEUP Datasheet(HTML) 7 Page - Maxim Integrated Products |
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7 / 34 page  Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs _______________________________________________________________________________________ 7 TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) (DVDD = 1.8V to 2.7V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Frequency fSCLK 1.8V < DVDD < 2.7V 10 MHz SCLK Pulse-Width High tCH (Note 7) 40 ns SCLK Pulse-Width Low tCL (Note 7) 40 ns CS Fall to SCLK Rise Setup Time tCSS 20 ns SCLK Rise to CS Rise Hold Time tCSH 5ns SCLK Rise to CS Fall Setup TIme tCS0 10 ns DIN to SCLK Rise Setup Time tDS 20 ns DIN to SCLK Rise Hold Time tDH 5ns SCLK Rise to DOUTDC1 Valid Propagation Delay tDO1 CL = 20pF, UPIO_ = DOUTDC1 mode 60 ns SCLK Fall to DOUT_ Valid Propagation Delay tDO2 CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode 60 ns CS Rise to SCLK Rise Hold Time tCS1 MICROWIRE and SPI modes 0 and 3 20 ns CS Pulse-Width High tCSW 90 ns UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance 200 ns DOUTRB Tri-State Time from CS Rise tDRBZ CL = 20pF, from rising edge of CS to UPIO_ in high impedance 40 ns DOUTRB Tri-State Enable Time from 8th SCLK Rise tZEN CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state 40 ns LDAC Pulse-Width Low tLDL Figure 5 40 ns LDAC Effective Delay tLDS Figure 6 200 ns CLR, MID, SET Pulse-Width Low tCMS Figure 5 40 ns GPO Output Settling Time tGP Figure 6 200 ns GPO Output High-Impedance Time tGPZ 200 ns |
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Similar Description - MAX5580AEUP |
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