 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
72291L10TFG Datasheet(PDF) 3 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
72291L10TFG Datasheet(HTML) 3 Page - Integrated Device Technology |
|
|
3 / 26 page  3 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 DESCRIPTION (CONTINUED) Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO DATA OUT (Q0 - Qn) DATA IN (D0 - Dn) MASTER RESET ( MRS) READ CLOCK (RCLK) READ ENABLE ( REN) OUTPUT ENABLE ( OE) EMPTY FLAG/OUTPUT READY ( EF/OR) PROGRAMMABLE ALMOST-EMPTY ( PAE) WRITE CLOCK (WCLK) WRITE ENABLE ( WEN) LOAD ( LD) FULL FLAG/INPUT READY ( FF/IR) PROGRAMMABLE ALMOST-FULL ( PAF) IDT 72281 72291 PARTIAL RESET ( PRS) FIRST WORD FALL THROUGH/SERIAL INPUT (FWFT/SI) RETRANSMIT ( RT) 4675 drw 03 HALF-FULL FLAG ( HF) SERIAL ENABLE( SEN) FWFT mode. HF, PAE andPAFarealwaysavailableforuse,irrespectiveof timingmode. PAE and PAF can be programmed independently to switch at any point in memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127 or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith the LD pin during Master Reset. For serialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serialorparalleloffsetloadinghasbeenselected. DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023 withserialprogramming. Theflagsareupdatedaccordingtothetimingmode anddefaultoffsetsselected. The Partial Reset (PRS) also sets the read and write pointers to the first locationofthememory. However,thetimingmode,partialflagprogramming method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogrammingpartialflagswouldbeundesirable. TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit operation by setting the read pointer to the first location of the memory array. If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs)willimmediatelytakethedeviceoutofthepowerdownstate. The IDT72281/72291 are fabricated using high speed submicron CMOS technology. |
Similar Part No. - 72291L10TFG |
|
Similar Description - 72291L10TFG |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
