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723652L12PFG Datasheet(PDF) 11 Page - Integrated Device Technology |
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723652L12PFG Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 29 page 11 COMMERCIALTEMPERATURERANGE IDT723652/723662/723672 CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 for the IDT723652, IDT723662, or IDT723672, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Validprogrammingvaluesfortheregistersrangesfrom1to2,044forthe IDT723652; 1 to 4,092 for the IDT723662; and 1 to 8,188 for the IDT723672. After all the offset registers are programmed from port A, the port B Full/Input Ready flag ( FFB/IRB) is set HIGH, and both FIFOs begin normal operation. See Figure 3 for relevant offset register parallel programming timing diagram. FIFO WRITE/READ OPERATION ThestateoftheportAdata(A0-A35)outputsiscontrolledbyportAChipSelect ( CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedancestatewheneither CSAorW/RAisHIGH. TheA0-A35outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSAisLOW,W/RAisLOW,ENA is HIGH, MBA is LOW, and EFA/ORAisHIGH(seeTable2). FIFOreadsand writes on port A are independent of any concurrent port B operation. Write and Read cycle timing diagrams for Port A can be found in Figure 4 and 7. The port B control signals are identical to those of port A with the exception thattheportBWrite/Readselect( W/RB)istheinverseoftheportAWrite/Read select(W/ RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe port B Chip Select ( CSB) and port B Write/Read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB is HIGH orW/RBis LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transitionofCLKBwhen CSBisLOW,W/RBisLOW,ENBisHIGH,MBBisLOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO reads and writes on port B are independent of any concurrent port A operation. Write and Read cycle timing diagrams for Port B can be found in Figure 5 and 6. ThesetupandholdtimeconstraintstotheportClocksfortheportChipSelects andWrite/Readselectsareonlyforenablingwriteandreadoperationsandare notrelatedtohigh-impedancecontrolofthedataoutputs. IfaportenableisLOW during a clock cycle, the port’s Chip Select and Write/Read select may change states during the setup and hold time window of the cycle. WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW, the next word written is automatically sent to the FIFO’s output register by the LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH. When the Output Ready flag is HIGH, subsequent data is clocked to the output registers only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in IDT Standard mode, the first word will cause the Empty Flag to change state on the second LOW-to-HIGH transition of the Read Clock. The data word will not be automatically sent to the output register. Instead, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O Port Function H X X X X High-Impedance None L L L X X Input None LL H L ↑ Input FIFO2 write LL H H ↑ Input Mail2 write L H L L X Output None LH H L ↑ Output FIFO1 read L H L H X Output None LH H H ↑ Output Mail1 read (set MBF1 HIGH) TABLE 3 — PORT B ENABLE FUNCTION TABLE TABLE 2 — PORT A ENABLE FUNCTION TABLE CSA W/ RA ENA MBA CLKA Data A (A0-A35) I/O Port Function H X X X X High-Impedance None L H L X X Input None LH H L ↑ Input FIFO1 write LH H H ↑ Input Mail1 write L L L L X Output None LL H L ↑ Output FIFO2 read L L L H X Output None LL H H ↑ Output Mail2 read (set MBF2 HIGH) |
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