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MT5C1001DCJ-70 Datasheet(PDF) 2 Page - Austin Semiconductor |
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MT5C1001DCJ-70 Datasheet(HTML) 2 Page - Austin Semiconductor |
2 / 13 page SRAM MT5C1001 Limited Availability Austin Semiconductor, Inc. MT5C1001 Rev. 2.0 2/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 FUNCTIONAL BLOCK DIAGRAM TRUTHTABLE 1,048,576-BIT MEMORY ARRAY 512 rows x 2048 columns VCC Vss D Q CE\ WE\ A6 A5 A4 A3 A15 A14 A13 A8 A7 COLUMN DECODER A2 A1 A16 A0 A17 A18 A19 A10 A9 A12 A11 POWER DOWN MODE CE\ WE\ OUTPUT POWER STANDBY H X HIGH-Z STANDBY READ L H Q ACTIVE WRITE L L HIGH-Z ACTIVE PIN ASSIGNMENTS PIN ASSIGNMENT A0-A19 Address Inputs WE\ Write Enable CE\ Chip Enable D Data Input Q Data Output NC No Connection VCC +5V Power Supply VSS Ground |
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