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PC87415 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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PC87415 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 42 page  TLF12497 PRELIMINARY March 1996 PC87415 PCI-IDE DMA Master Mode Interface Controller 10 General Description The Enhanced PCI-IDE Interface is a single-chip controller packaged in a 100-pin PQFP It provides 2 IDE channels for interfacing up to 4 IDE drives or 2 IDE drives and CD-ROM directly on the PCI Local bus An enhanced DMA controller on-chip increases system performance by providing full scattergather data transfers between IDE devices and sys- tem memory without CPU intervention Four levels of both write posting and read prefetching per channel allow the host CPU to run concurrently with IDE cycles Programma- ble timing functions provide maximum flexibility of timing pa- rameters per drive for optimizing the data transfer rate per drive Both PC compatible addressing and PCI compliant addressing are supported by re-mapping the base address- es A power control feature allows turning off power to the IDE cables The Enhanced PCI-IDE Interface connection to the PCI bus is virtually ‘‘glue-less’’ with only one additional TTL data buffer (optional) This high-integration solution reduces component count eases board design reduces cost and increases reliability The Enhanced PCI-IDE supports faster ATA devices using PIO modes 1 2 3 and 4 as well as DMA modes 0 1 and 2 It comes with a full suite of software drivers for DOS 50 – 6x Windows 3x Windows 95 Windows NTTM OS2 2x Novell NetWareTM 31x – 4x and SCO UNIX 3x TRI-STATE is a registered trademark of National Semiconductor Corporation WATCHDOGTM is a trademark of National Semiconductor Corporation Novell is a registered trademark of Novell Inc NetWareTM is a trademark of Novell Inc Unix is a registered trademark of ATT Bell Laboratories Windows and Windows 95 are registered trademarks of Microsoft Corporation Windows NTTM is a trademark of Microsoft Corporation 20 Features Y PCI bus interface for up to 4 IDE devices Y 33 MHz 32-bit PCI bus data path with full parity error reporting Y 167 MBytesec maximum IDE transfer rate Y Support for 2 IDE channels ( 2 IDE devices per chan- nel) Y Primary or secondary IDE addressing (1F0x170x) in PC compatible mode Y Re-mappable base registers for full PCI compliance Y Concurrent channel operation (PIO DMA modes) Y 4 Double Word write FIFO per channel Y 4 Double Word read prefetch FIFO per channel Y Enhanced DMA mode with scattergather capability Y ANSI ATA Modes 0 through 4 PIO support (internal DMA not selected) Y IORDY handshaking for PIO Y ANSI ATA Modes 0 through 2 Multiword DMA support (internal DMA selected) Y Individually programmable command and recovery tim- ing for reads and writes per channeldrive for com- mand control and data Y Individually programmable data sector size for read pre- fetches per channel Y PC compatible interrupt routing of IRQ14 and IRQ15 Y Hardware and software chip enabledisable Y Optional Power Control for IDE Drives Y Fully static logic design Y 100-pin PQFP package TLF12497 – 1 FIGURE 1 The PC87415 in a PCI Based System C1996 National Semiconductor Corporation RRD-B30M46Printed in U S A http www nationalcom |
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