SC16C750B datasheet(9/44 Pages) PHILIPS

Part #	SC16C750B

Description	5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Product data

Rev. 03 — 13 December 2004

9 of 44

9397 750 14453

6.

Functional description

The SC16C750B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data

stream into parallel data that is required with digital data systems. Synchronization for

the serial data stream is accomplished by adding start and stop bits to the transmit

data to form a data character (character orientated protocol). Data integrity is insured

by attaching a parity bit to the data character. The parity bit is checked by the receiver

for any transmission bit errors. The SC16C750B is fabricated with an advanced

CMOS process to achieve low drain power and high speed requirements.

The SC16C750B is an upward solution that provides 64 bytes of transmit and receive

FIFO memory, instead of none in the 16C450, or 16 in the 16C550. The SC16C750B

is designed to work with high speed modems and shared network environments that

require fast data processing time. Increased performance is realized in the

SC16C750B by the larger transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable levels of FIFO trigger interrupt and automatic hardware ﬂow control is

uniquely provided for maximum data throughput performance, especially when

operating in a multi-channel environment. The combination of the above greatly

reduces the bandwidth requirement of the external controlling CPU, increases

performance, and reduces power consumption.

The SC16C750B is capable of operation up to 3 Mbit/s with a 48 MHz external clock

input (at 5 V).

The rich feature set of the SC16C750B is available through internal registers.

Automatic hardware ﬂow control, selectable transmit and receive FIFO trigger level,

selectable TX and RX baud rates, modem interface controls, and a sleep mode are

some of these features.

6.1 Internal registers

The SC16C750B provides 12 internal registers for monitoring and control. These

registers are shown in Table 3. These twelve registers are similar to those already

available in the standard 16C550. These registers function as data holding registers

(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register

(FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),

and a user accessible scratchpad register (SPR). Register functions are more fully

described in the following paragraphs.

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Similar Description - SC16C750B

Manufacturer	Part #	Datasheet	Description
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