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X5043M8I Datasheet(PDF) 7 Page - Xicor Inc. |
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X5043M8I Datasheet(HTML) 7 Page - Xicor Inc. |
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7 / 20 page  X5043/X5045 Characteristics subject to change without notice. 7 of 20 REV 1.1.2 5/29/01 www.xicor.com Table 2. Device Protect Matrix Figure 6. Read Status Register Sequence Figure 7. Write Status Register Sequence WREN CMD (WEL) Device Pin (WP) Memory Block Status Register Protected Area Unprotected Area (BL0, BL1, WD0, WD1) 0 x Protected Protected Protected x 0 Protected Protected Protected 1 1 Protected Writable Writable 0123456789 10 11 12 13 14 76543210 Data Out CS SCK SI SO MSB High Impedance Instruction 15 0123456789 CS SCK SI SO High Impedance Instruction Data Byte 7654 32 10 10 11 12 13 14 15 Read Memory Array When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 8-bit address. Bit 3 of the READ instruction selects the upper or lower half of the device. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to pro- vide clock pulses. The address is automatically incre- mented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $000 allowing the read cycle to be continued indefi- nitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 8). |
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