Semiconductor Group

133

Circuit Description

The sound intermediate frequencies contained in the baseband of a demodulated FM satellite

signal can lie between 5 and 9 MHz. This band of frequencies is applied ready filtered to the input

of the converter mixer. The purpose of this mixer is to convert the different sound IFs in the

baseband to fixed output frequencies (eg 10.7/10.52 MHz). These frequencies are then fed by

external filters to the inputs of the three sound IF-amplifiers.

The VCO of the mixer can be continuously tuned between 14.5 and 20 MHz in 10-kHz increments

with crystal accuracy by means of a PLL-circuit.

The setting of the programmable divider and the cutting in and out of the sound IF-amplifiers are

Pin 5 (CA) offers two switchable chip addresses to enable parallel operation of two devices.

All pins are guarded against electrostatic discharge. SCL and SDA include special protective

structures to permit continued bus operation when the device is switched off.

PLL

The VCO-signal, DC coupled internally, is applied to the PLL-input. It passes through a

programmable divider (

(

f

oscillator whose signal is divided by 400.

The phase detector has a charge-pump push-pull current output. If the negative edge of the divided

VCO-signal appears before the negative edge of the reference signal, the current source I+ will

pulse for the duration of the phase difference. In the reverse case it is the current sink I–. If both

signals are in-phase, the output is high-impedance and the PLL is locked in. The current pulses are

filtered by means of an integrator (internal operational amplifier with external RC-circuitry).

The pump current can be switched between the two values 1 and 5 by software with a control bit 5I.

This permits a change in the control response during and after the lock-in state.

Information is exchanged between the processor and the sound IF-device on an asynchronous

bidirectional data bus. The timing for this comes from the processor (input SCL), while pin SDA-

functions as an input or output depending on the direction of the data (open collector; external

pull-up resistor).

according to their function. When the bus is not busy, both lines are in marking state (SDA, SCL are

high). Each telegram begins with the start condition: SDA goes low while SCL remains high. All

further exchanges of information are while SCL is low and are read by the controller with the positive

clock edge. If SDA goes high while the clock is high, the PLL recognizes this as a stop condition and

thus the end of the telegram.

For what follows, refer to the table of logic assignments below.

All telegrams are transferred byte by byte, followed by a ninth clock pulse during which the controller

pulls the SDA-line to low (i.e. acknowledge condition). The first byte consists of seven address bits

with which the processor selects the PLL from among several peripheral devices (chip select). The

TDA 6160-2S