AD7183 datasheet(7/40 Pages) AD

Part #	AD7183

Description	Advanced Video Decoder with 10-Bit ADC and Component Input Support

Download	40 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

Logo

7 / 40 page

REV. 0

ADV7183

–7–

PIN FUNCTION DESCRIPTIONS

Mnemonic

Input/Output

Function

1

VS/VACTIVE

O

VS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an

output signal that indicates a vertical sync with respect to the YUV pixel

data. The active period of this signal is six lines of video long. The polarity

of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =

1, 0 or 0, 1) is an output signal that is active during the active/viewable

period of a video field. The polarity of VACTIVE is controlled by PVS bit.

2

HS/HACTIVE

O

HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a

programmable horizontal sync output signal. The rising and falling edges

can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity

of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0] =

1, 0 or 0, 1) is an output signal that is active during the active/viewable

period of a video line. The active portion of a video line is programmable on

the ADV7183. The polarity of HACTIVE is controlled by PHS bit.

3, 14

DVSSIO

G

Digital I/O Ground

4, 15

DVDDIO

P

Digital I/O Supply Voltage (3.3 V)

5–8, 19–24,

P15–P0

O

Video Pixel Output Port. 8-bit multiplexed YCrCb pixel port (P15–P8),

32, 33, 73–76

16-bit YCrCb pixel port (P15–P8 = Y and P7–P0 = Cb,Cr).

9, 31, 71

DVSS1–3

G

Ground for Digital Supply

10, 30, 72

DVDD1–3

P

Digital Supply Voltage (3.3 V)

11

AFF

O

Almost Full Flag. A FIFO control signal indicating when the FIFO has

reached the almost full margin set by the user (use FFM[4:0]). The polarity

of this signal is controlled by the PFF bit.

12

HFF/QCLK/GL

I/O

Half Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO

control signal that indicates when the FIFO is half full. The QCLK

(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when

using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function

(Genlock output) is a signal that contains a serial stream of data that contains

information for locking the subcarrier frequency. The polarity of HFF signal

is controlled by PFF bit.

13

AEF

O

Almost Empty Flag. A FIFO control signal, it indicates when the FIFO

has reached the almost empty margin set by the user (use FFM[4:0]). The

polarity of this signal is controlled by PFF bit.

16

CLKIN

I

Asynchronous FIFO Clock. This asynchronous clock is used to output

data onto the P19-P0 bus and other control signals.

17, 18, 34, 35

GPO[3:0]

O

General-Purpose Outputs controlled via I

2C

25

LLCREF

O

Clock Reference Output. This is a clock qualifier distributed by the inter-

nal CGC for a data rate of LLC2. The polarity of LLCREF is controlled

by the PLLCREF bit.

26

LLC2

O

Line-Locked Clock System Output Clock/2 (13.5 MHz)

27

LLC1/PCLK

O

Line-Locked Clock System Output Clock. A dual-function pin (27 MHz

± 5%)

or a FIFO output clock ranging from 20 MHz to 35 MHz.

28

XTAL1

O

Second terminal for crystal oscillator; not connected if external clock

source is used.

29

XTAL

I

Input terminal for 27 MHz crystal oscillator or connection for external

oscillator with CMOS-compatible square wave clock signal

36

PWRDN

I

Power-Down Enable. A logical low will place part in a power-down status.

37

ELPF

I

This pin is used for the External Loop Filter that is required for the LLC PLL.

38

PVDD

P

39

PVSS

G

Similar Part No. - AD7183

Manufacturer	Part #	Datasheet	Description
Analog Devices	AD71028	427Kb / 20P	Dual Digital BTSC Encoder with Integrated DAC REV. 0
	AD71028JST	427Kb / 20P	Dual Digital BTSC Encoder with Integrated DAC REV. 0
	AD71028JSTRL	427Kb / 20P	Dual Digital BTSC Encoder with Integrated DAC REV. 0
	AD71028	427Kb / 20P	Dual Digital BTSC Encoder with Integrated DAC REV. 0
	AD71056	412Kb / 20P	Energy Metering IC with Integrated Oscillator and Reverse Polarity Indication REV. A

More results

Similar Description - AD7183

Manufacturer	Part #	Datasheet	Description
Renesas Technology Corp	TW9912	183Kb / 2P	NTSC/PAL/SECAM Video Decoder with Component Input and Progressive Output Support
NXP Semiconductors	SAA7118	665Kb / 169P	Multistandard video decoder with adaptive comb filter and component video input 2001 May 30
	SAF7118	950Kb / 173P	Multistandard video decoder with adaptive comb filter and component video input 2004 Jul 22
	SAA7154E	420Kb / 90P	Multistandard video decoder with comb filter, component input and RGB output Rev. 02-6 December 2007
Toshiba Semiconductor	TC90106FG	726Kb / 18P	Multi System Video Decoder for Component input
Renesas Technology Corp	TW9906	201Kb / 2P	3x10-bit Multi-Standard Comb Filter Video Decoder with YCbCr Component Input
List of Unclassifed Man...	BIT1628A	47Kb / 1P	10-Bit Digital Video Decoder with OSD and T-CON
Analog Devices	ADV7182	1Mb / 96P	10-Bit, SDTV Video Decoder with Differential Inputs REV. A
Texas Instruments	TVP5160	1Mb / 111P	[Old version datasheet] NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder
STMicroelectronics	STE5588	197Kb / 3P	DVD and DVB decoder for video and audio with DVD audio support

More results

AD7183 Datasheet(PDF) 7 Page - Analog Devices

AD7183 Datasheet(HTML) 7 Page - Analog Devices

Similar Part No. - AD7183

Similar Description - AD7183

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL