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LOG101

2

SBOS242B

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

LOG101AID

SO -8

D

–5

°C to +75°C

LOG101

LOG101AID

Rails, 100

"

"""

"

LOG101AIDR

Tape and Reel, 2500

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

Supply Voltage, V+ to V– .................................................................... 36V

Input Voltage .................................................... (V–) – 0.5 to (V+) + 0.5V

Input Current ...................................................................................

±10mA

Operating Temperature .................................................... –40

°C to +85°C

Storage Temperature ..................................................... –55

°C to +125°C

Junction Temperature .................................................................... +150

°C

Lead Temperature (soldering, 10s) ............................................... +300

°C

NOTES: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability. (2) Short-circuit to ground.

PIN DESCRIPTION

ELECTRICAL CHARACTERISTICS

Top View

SO

I

2

NC

GND

V–

NC = No Internal Connection

LOG101

I

1

NC

V

OUT

V+

8

7

6

5

1

2

3

4

LOG101AID

PARAMETER

CONDITION

MIN

TYP

MAX

UNITS

CORE LOG FUNCTION

Initial

1nA to 100

µA (5 decades)

0.01

0.2

%

100pA to 3.5mA (7.5 decades)

0.06

%

over Temperature

1nA to 100

0.0001

%/

0.0005

%/

Initial Value

1nA to 100

µA

1

V/decade

Gain Error

1nA to 100

µA

0.15

±1%

vs Temperature

0.003

0.01

%/

INPUT, A1 and A2

Offset Voltage

±0.3

±1.5

mV

vs Temperature

µV/

vs Power Supply (PSRR)

5

50

µV/V

Input Bias Current

±5pA

vs Temperature

Doubles Every 10

Voltage Noise

f = 10Hz to 10kHz

3

µVrms

f = 1kHz

30

nV/

√Hz

Current Noise

f = 1kHz

4

fA/

√Hz

Common-Mode Voltage Range (Positive)

(V+) – 2

(V+) – 1.5

V

(Negative)

(V–) + 2

(V–) + 1.2

V

Common-Mode Rejection Ratio (CMRR)

105

dB

±3

±15

mV

vs Temperature

Full-Scale Output (FSO)

(V–) + 1.2

(V+) – 1.5

V

Short-Circuit Current

±18

mA